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參數(shù)資料
| 型號： | MTD20N03HDL |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 1.5 A Switch-Mode Power Supply with Linear Regulator |
| 中文描述： | 1.5開關(guān)模式電源，線性穩(wěn)壓器 |
| 文件頁數(shù)： | 29/38頁 |
| 文件大小： | 739K |
| 代理商： | MTD20N03HDL |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
29
34701
TYPICAL APPLICATION
TYPICAL APPLICATION
BUCK REGULATOR CONTROL CIRCUIT
The 34701 buck regulator utilizes a PWM Voltage Mode
topology with Feed-Forward to achieve an excellent line and
load regulation. The control circuit block diagram is shown in
Figure 29
.
Figure 29. Buck Regulator Control Circuit
The integrated 40 pF capacitor C
F
charged through the
external resistor R4 provides the feed-forward ramp
waveform, the amplitude of which is proportional to the input
voltage, thus providing the feed-forward function.
Figure 30
shows the Bode plot of the 34701 buck regulator
control loop gain and phase versus frequency.
The first double pole on the Bode plot is created by the
buck regulator output L-C filter, and its frequency can be
calculated as:
Where C
O
is the value of the buck output capacitor and L
is the inductance value of the output filter inductor L.
The frequency of the compensating zero can be calculated
as follows.
The Feed-Forward implemented by resistor R4 and
integrated capacitor C
F
creates a pole in the overall loop
transfer function, the frequency of which can be calculated
from the following formula.
Where V
Ref
is the buck regulator reference voltage
(V
Ref
= 0.8 V typ.) at the INV terminal,
V
IN
is the buck regulator input voltage,
V
m1
is the ramp generated by the internal ramp
generator (V
m1
= 0.5 V typ.).
.
Figure 30. Buck Control Loop Bode Plot
L
f
LC
2
π
C
O
L
----------1
=
f
z c
( )
2
C2 R1
R3
+
)
-------------------1
=
f
p FF
)
V
R4C
F
f
sw
-1
IN
-V
V
Ref
)
V
m1
+
×
----------------------------–
2
R4C
F
---------1
×
=
Φ
m
0
-20
20
-40
-270
-360
-180
10
100
1000
1.0
Frequency [kHz]
Gain
[dB]
fLC
fz(c)
fBW
fz(ESR)fp(FF)
fp(c)
10000
Phase
[Deg.]
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