參數(shù)資料
型號: MTD20N03HDL
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 1.5 A Switch-Mode Power Supply with Linear Regulator
中文描述: 1.5開關模式電源,線性穩(wěn)壓器
文件頁數(shù): 12/38頁
文件大?。?/td> 739K
代理商: MTD20N03HDL
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
34701
DYNAMIC ELECTRICAL CHARACTERISTICS
Boost Regulator
Boost Regulator MOSFET Maximum ON Time
(20)
t
ON
24
μ
s
Boost Regulator Control Loop Propagation Delay
(20)
t
BST_PD
50
ns
Boost Switching Node VBD Rise Time
(20)
IBST = 20 mA
t
B_RISE
5.0
ns
Boost Switching Node VBD Fall Time
(20)
IBST = 20 mA
t
B_FALL
3.0
ns
Linear Regulator (LDO)
Fault Condition Time-Out
t
FAULT
7.0
10
15
ms
Retry Timer Cycle
t
Ret
70
100
150
ms
Reset Monitor (
RST
)
Monitoring LFB Terminal Delay
t
D_RST_LFB
12
28
μ
s
Monitoring INV Terminal Delay
t
D_RST_INV
12
28
μ
s
SCA, SCL Terminal, I
2
C Bus (Standard)
SCL Clock Frequency
(20)
f
SCL
100
kHz
Bus Free Time Between a STOP and a START Condition
(20)
t
BUF
4.7
μ
s
Hold Time (Repeated) START Condition (After this period, the first clock
pulse is generated.)
(20)
t
HD-STA
4.0
μ
s
Low Period of the SCL Clock
(20)
t
LOW
4.7
μ
s
High Period of the SCL Clock
(20)
t
HIGH
4.0
μ
s
SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10 pF to 400
pF, 3.0 mA Sink Current
(20)
,
(22)
t
F
250
ns
Setup Time for a Repeated START Condition
(20)
t
SU-STA
4.7
μ
s
Data Hold Time for I
2
C Bus Devices
(20)
,
(21)
t
HD-DAT
0.0
μ
s
Data Setup Time
(20)
t
SU-DA
T
250
ns
Setup Time for STOP Condition
(20)
t
SU-STO
4.0
μ
s
Capacitive Load for Each Bus Line
(20)
C
B
400
pF
Notes
20.
21.
Design information only. This parameter is not production tested.
The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the V
IH_MIN
of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
VIH is High Level Voltage on I
2
C bus lines and VIL is Low Level Voltage on I
2
C bus lines
22.
Table 4.
Characteristics noted under conditions -40°C
T
A
85
°
C unless otherwise noted. Input voltages VIN1 = VIN2
= 3.3 V using
the typical application circuit (see
Figures 33
) unless otherwise noted.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
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