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參數(shù)資料
| 型號(hào)： | MTD15N06VL1 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | JFETs |
| 英文描述： | 15 A, 60 V, 0.085 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | DPAK-3 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 106K |
| 代理商： | MTD15N06VL1 |
MTD15N06VL
http://onsemi.com
7
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
DPAK
5.80
0.228
2.58
0.101
1.6
0.063
6.20
0.244
3.0
0.118
6.172
0.243
mm
inches
SCALE 3:1
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a
surface mount device is determined by TJ(max), the
maximum rated junction temperature of the die, RqJA, the
thermal resistance from the device junction to ambient, and
the operating temperature, TA. Using the values provided
on the data sheet, PD can be calculated as follows:
PD =
TJ(max) TA
RqJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device. For a
DPAK device, PD is calculated as follows.
PD =
175
°C 25°C
71.4
°C/W
= 2.1 Watts
The 71.4
°C/W for the DPAK package assumes the use of
0.5 sq. in. source pad on a glass epoxy printed circuit board
to achieve a power dissipation of 2.1 W. There are other
alternatives to achieving higher power dissipation from the
surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the
power dissipation can be increased. Although one can
almost double the power dissipation with this method, one
will be giving up area on the printed circuit board which
can defeat the purpose of using surface mount technology.
For example, a graph of RqJA versus drain pad area is
shown in Figure 15.
Figure 15. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
2.1 Watts
Board Material = 0.0625
″
G10/FR4, 2 oz Copper
80
100
60
40
20
10
8
6
4
2
0
3.6 Watts
6.0 Watts
TA = 25°C
A, AREA (SQUARE INCHES)
T
O
AMBIENT
(
C/W)°
R
JA
,THERMAL
RESIST
ANCE,
JUNCTION
θ
SOLDER STENCIL GUIDELINES
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MTD15N06VLT4 | 15 A, 60 V, 0.085 ohm, N-CHANNEL, Si, POWER, MOSFET |
| MTD15N06VL-1 | 15 A, 60 V, 0.085 ohm, N-CHANNEL, Si, POWER, MOSFET |
| MTD15N06VL | 15 A, 60 V, 0.085 ohm, N-CHANNEL, Si, POWER, MOSFET |
| MTD15N06VT4 | 15 A, 60 V, 0.12 ohm, N-CHANNEL, Si, POWER, MOSFET |
| MTD1N50E-T4 | 1 A, 500 V, 5 ohm, N-CHANNEL, Si, POWER, MOSFET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MTD15N06VLT4 | 制造商:ON Semiconductor 功能描述:Trans MOSFET N-CH 60V 15A 3-Pin(2+Tab) DPAK T/R |
| MTD15N06VT4 | 制造商:ON Semiconductor 功能描述:Trans MOSFET N-CH 60V 15A 3-Pin(2+Tab) DPAK T/R |
| MTD1N40 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:POWER FIELD EFFECT TRANSISTOR |
| MTD1N50E | 制造商:Motorola Inc 功能描述: |
| MTD1N60E | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:TMOS POWER FET 1.0 AMPERE 600 VOLTS RDS(on) = 8.0 OHM |
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