- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385641 > MT9VDDT3272A (Micron Technology, Inc.) DDR SDRAM DIMM PDF資料下載
參數(shù)資料
| 型號： | MT9VDDT3272A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DDR SDRAM DIMM |
| 中文描述： | DDR SDRAM的內存 |
| 文件頁數(shù)： | 9/29頁 |
| 文件大小： | 542K |
| 代理商： | MT9VDDT3272A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
9
2003 Micron Technology. Inc.
Burst Length
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being program-
mable, as shown in Figure 5, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-A9 when the burst length is set to two,
by A2–A9 when the burst length is set to four and by
A3–A9 when the burst length is set to eight (where A9 is
the most significant column address bit for a given
configuration). The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. The programmed burst length
applies to both read and write bursts.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 10.
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS
Latency Diagram, on page 10.
If a READ command is registered at clock edge
n
,
and the latency is
m
clocks, the data will be available
nominally coincident with clock edge
n
+
m
. Table 7,
CAS Latency (CL) Table, on page 10, indicates the
operating frequencies at which each CAS latency set-
ting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Figure 5: Mode Register Definition
Diagram
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7–A11
(128MB), or A7–A12 (256MB) each set to zero, and bits
A0–A6 set to the desired values. A DLL reset is initiated
by issuing a MODE REGISTER SET command with bits
A7 and A9–A11 (128MB), or A7 and A9–A12 (256MB)
each set to zero, bit A8 set to one, and bits A0–A6 set to
the desired values. Although not required by the
Micron device, JEDEC specifications recommend
when a LOAD MODE REGISTER command is issued to
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
0
1
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
-
Valid
Valid
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
Reserved
Reserved
Reserved
2.5
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency BT
0*
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8 M7
Operating Mode
A10
A12 A11
BA0
BA1
10
11
12
13
0*
14
* M14 and M13 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
M9
M10
M12 M11
Burst Length
CAS Latency BT
0*
0*
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
Operating Mode
A10
A11
BA0
BA1
10
11
12
13
* M13 and M12 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
128MB Module
256MB Module
相關PDF資料 |
PDF描述 |
|---|---|
| MTB2P50E | Power MOSFET 2 Amps, 500 Volts(2A, 500V功率MOSFET) |
| MTB50P03HDL | Power MOSFET 50 Amps, 30 Volts, Logic Level(50A, 30V, D2PAK, P溝道功率MOSFET) |
| MTD20N06HDLT4 | Power MOSFET 20 Amps, 60 Volts, Logic Level N−Channel DPAK |
| MTD20N06HDLT4G | Power MOSFET 20 Amps, 60 Volts, Logic Level N−Channel DPAK |
| MTD6N15 | Power Field Effect Transistor DPAK for Surface Mount(功率場效應晶體管) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT9VDDT3272AG-202B1 | 制造商:Micron Technology Inc 功能描述:DRAM MOD DDR SDRAM 2.25GBIT 184UDIMM - Trays |
| MT9VDDT3272AG-262G4 | 功能描述:MODULE SDRAM DDR 256MB 184DIMM RoHS:否 類別:存儲卡，模塊 >> 存儲器 - 模塊 系列:- 標準包裝:100 系列:- 存儲器類型:SDRAM 存儲容量:1GB 速度:133MHz 特點:- 封裝/外殼:168-DIMM |
| MT9VDDT3272AG-265B1 | 制造商:Micron Technology Inc 功能描述:DRAM MOD DDR SDRAM 2.25GBIT 184UDIMM - Trays |
| MT9VDDT3272AG-265C4 | 制造商:Micron Technology Inc 功能描述:DRAM MOD DDR SDRAM 2.25GBIT 184UDIMM - Trays |
| MT9VDDT3272AG-265G4 | 功能描述:MODULE SDRAM DDR 256MB 184DIMM RoHS:否 類別:存儲卡，模塊 >> 存儲器 - 模塊 系列:- 標準包裝:100 系列:- 存儲器類型:SDRAM 存儲容量:1GB 速度:133MHz 特點:- 封裝/外殼:168-DIMM |
發(fā)布緊急采購，3分鐘左右您將得到回復。