參數(shù)資料
型號(hào)： MT9VDDT3272A
廠商： Micron Technology, Inc.
英文描述： DDR SDRAM DIMM
中文描述： DDR SDRAM的內(nèi)存
文件頁(yè)數(shù)： 4/29頁(yè)
文件大?。?/td> 542K
代理商： MT9VDDT3272A
128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4
2003 Micron Technology. Inc.
Table 5:
Refer to Pin Assignment Tables on page 3 for pin number and symbol information
Pin Descriptions
PIN NUMBERS
1
63, 65, 154
SYMBOL
VREF
WE#, CAS#, RAS#
TYPE
Input
Input
DESCRIPTION
SSTL_2 reference voltage.
Command Inputs: WE#, RAS#, and CAS# (along with S#)
define the command being entered.
Clocks: CK and CK# are differential clock inputs. All
address and control input signals are sampled on the
crossing of the positive edge of CK and negative edge of
CK#. Output data (DQs and DQS) is referenced to the
crossings of CK and CK#.
Clock Enable: CKE activates (HIGH) and deactivates (LOW)
internal clock signals, device input buffers, and output
drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device
banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any
device bank). CKE0 is synchronous for all functions except
for disabling outputs, which is achieved asynchronously.
CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE)
are disabled during POWERDOWN. Input buffers
(excluding CKE) are disabled during SELF REFRESH. CKE is
an SSTL_2 input but will detect an LVCMOS LOW level
after V
DD
is applied.
Chip Select: S# enables (registered LOW) and disable
(registered HIGH) the command decoder. All commands
are masked when S# is registered HIGH. S# is considered
part of the command code.
Bank Addresses: BA0 and BA1 define to which device
bank an ACTIVE, READ, WRITE or PRECHARGE command
is being applied.
Address Inputs: Sampled during the ACTIVE command
(row-address) and READ/WRITE command (column-
address, with A10 defining auto precharge) to select one
location out of the memory array in the respective device
device bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies
to one device bank (A10 LOW) or all device banks (A10
HIGH). The address inputs also provide the op-code
during a MODE REGISTER SET command.
Serial Clock for Presence-Detect: SCL is used to
synchronize the presence-detect data transfer to and
from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Serial Presence-Detect Data: SDA is a bidirectional pin
used to transfer addresses and data into and out of the
presence- detect portion of the module.
Data I/Os: Check bits. ECC, one-bit error detection and
correction.
Data Strobes: Output with read data, input with write
data. Edge- aligned with read data, centered in write
data. Used to capture write data.
16, 17, 75, 76, 137, 138
CK0, CK0#, CK1,
CK1#, CK2, CK2#
Input
21
CKE0
Input
157
S0#
Input
52, 59
BA0, BA1
Input
27, 29, 32, 37, 41, 43, 48,
115
(256MB)
,
118, 122, 125,
130, 141
A0-A11
(128MB)
A0-A12
(256MB)
Input
92
SCL
Input
181, 182, 183
SA0-SA2
Input
91
SDA
Input/Output
44, 45, 49, 51, 134, 135,
142, 144
5, 14, 25, 36, 47, 56, 67, 78,
86, 97, 107, 119, 129, 140,
149, 159, 169, 177
CB0-CB7
Input/Output
DQS0-DQS17
Input/Output
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參數(shù)描述
MT9VDDT3272AG-202B1 制造商:Micron Technology Inc 功能描述:DRAM MOD DDR SDRAM 2.25GBIT 184UDIMM - Trays
MT9VDDT3272AG-262G4 功能描述:MODULE SDRAM DDR 256MB 184DIMM RoHS:否 類(lèi)別:存儲(chǔ)卡，模塊 >> 存儲(chǔ)器 - 模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 存儲(chǔ)器類(lèi)型:SDRAM 存儲(chǔ)容量:1GB 速度:133MHz 特點(diǎn):- 封裝/外殼:168-DIMM
MT9VDDT3272AG-265B1 制造商:Micron Technology Inc 功能描述:DRAM MOD DDR SDRAM 2.25GBIT 184UDIMM - Trays
MT9VDDT3272AG-265C4 制造商:Micron Technology Inc 功能描述:DRAM MOD DDR SDRAM 2.25GBIT 184UDIMM - Trays
MT9VDDT3272AG-265G4 功能描述:MODULE SDRAM DDR 256MB 184DIMM RoHS:否 類(lèi)別:存儲(chǔ)卡，模塊 >> 存儲(chǔ)器 - 模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 存儲(chǔ)器類(lèi)型:SDRAM 存儲(chǔ)容量:1GB 速度:133MHz 特點(diǎn):- 封裝/外殼:168-DIMM
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