參數(shù)資料
型號(hào): MT9173AE1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: Digital Subscriber Interface Circuit with RxSB Digital Network Interface Circuit with RxSB
中文描述: DATACOM, DIGITAL SLIC, PDIP24
封裝: 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-24
文件頁(yè)數(shù): 3/28頁(yè)
文件大?。?/td> 613K
代理商: MT9173AE1
MT9173/74
Data Sheet
3
Zarlink Semiconductor Inc.
Figure 3 - DV Port - 80 kbit/s (Modes 2, 3, 6)
14
16
DSTi/Di
Data ST-BUS In/Data In
(Digital). A 2.048 Mbit/s serial PCM/data input in DN mode.
In MOD mode this is a continuous bit stream at the bit rate selected.
15
17
F0o/RCK
Frame Pulse Out/Receive Bit Rate Clock
output (Digital). In DN mode a 244 ns
wide negative pulse indicating the end of the active channel times of the device to
allow daisy chaining. In MOD mode provides the receive bit rate clock to the system.
16
19
C4/TCK
Data Clock/Transmit Baud Rate Clock
(Digital). A 4.096 MHz TTL compatible clock
input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin
provides the transmit bit rate clock to the system.
Oscillator Output
. CMOS Output.
Oscillator Input
. CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical
Characteristics for OSC1 input requirements.
Precanceller Disable.
When held to Logic ’1’
,
the internal path from L
OUT
to the
precanceller is forced to V
Bias
thus bypassing the precanceller section. When logic ’0’,
the L
OUT
to the precanceller path is enabled and functions normally. An internal
pulldown (50 k
) is provided on this pin.
No Connection.
Leave open circuit
17
19
21
22
OSC2
OSC1
20
23
Precan
18
1,6,
18,
20,
25
24
NC
21
L
OUT
DIS
L
OUT
Disable.
When held to logic “1”, L
OUT
is disabled (i.e., output = V
Bias
). When
logic “0”, L
OUT
functions normally. An internal pulldown (50 k
) is provided on this pin.
Test Pin.
Connect to V
SS
.
Receive Signal
input (Analog).
Positive Power Supply
(+5 V) input.
22
23
24
26
27
28
TEST
L
IN
V
DD
Pin Description (continued)
Pin #
Name
Description
24
28
F0
C4
DSTi
DSTo
F0o
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B1
7
B1
6
B1
5
B1
4
B1
3
B1
2
B1
1
B1
0
B1
7
B1
7
Channel Time 0
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