參數(shù)資料
型號: MT9173AE1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: Digital Subscriber Interface Circuit with RxSB Digital Network Interface Circuit with RxSB
中文描述: DATACOM, DIGITAL SLIC, PDIP24
封裝: 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-24
文件頁數(shù): 17/28頁
文件大?。?/td> 613K
代理商: MT9173AE1
MT9173/74
Data Sheet
17
Zarlink Semiconductor Inc.
Figure 14 - Typical Connection Diagram - SLV/DN Mode, 160 kbit/s
** Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Parameters over recommended temperature & power supply voltage ranges.
Absolute Maximum Ratings
**
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
Parameter
Symbol
Min.
Max.
Units
1
Supply Voltage
V
DD
-0.3
7
V
2
Voltage on any pin (other than supply)
V
Max
-0.3
V
DD
+0.3
V
3
Current on any pin (other than supply)
I
Max
40
mA
4
Storage Temperature
T
ST
-65
+150
°
C
5
Package Power Dissipation
(Derate 16mW/
×
C above 75
°
C)
P
Diss
750
mW
Recommended Operating Conditions
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.*
Max.
Units
Test Conditions
1
Operating Supply Voltage
V
DD
4.75
5.00
5.25
V
2
Operating Temperature
T
OP
-40
+85
°
C
3
Input High Voltage (except OSC1)
V
IH
2.4
V
DD
V
for 400 mV noise margin
4
Input Low Voltage (except OSC1)
V
IL
0
0.4
V
for 400 mV noise margin
DV Port ST-BUS
CD Port ST-BUS
Master Clocks
Mode Select
Lines
+5 V
0.33
μ
F
0.33
μ
F
To hardware
DSTi
DSTo
CDSTi
CDSTo
F0
C4
MS0
MS1
MS2
V
Ref
V
Bias
RxSB
L
OUT
L
IN
OSC1
OSC2
R2 = 390
R1 = 47
C2’ = 1.5 nF
C2 = 22 nF
+5 V
D1 = D2 = MUR405
D2
2:1
{
{
{
1.0
μ
F
For 80 kbit/s: C2’ = 3.3 nF
C1 = 0.33
μ
F
68 Volts
(Typ)
2.5 Joules
0.02 Watt
Note:
Low leakage diodes (1 & 2) are required so
that the DC voltage at L
IN
a V
Bias
10.24 MHz XTAL
C3=33 pF=C4
Supply
MT9173/74
SYNC
Indicator
(optional)
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