參數(shù)資料
型號(hào)： MT90823AL
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： 3V Large Digital Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝： 14 X 20 MM, 2.80 MM HEIGHT, MO-112CC, MQFP-100
文件頁(yè)數(shù)： 6/46頁(yè)
文件大小： 663K
代理商： MT90823AL
MT90823
Data Sheet
6
Zarlink Semiconductor Inc.
35
8
5
N3
TDO
Test Serial Data Out (3.3 V Output):
JTAG serial data
is output on this pin on the falling edge of TCK. This pin
is held in high impedance state when JTAG scan is not
enabled.
36
9
6
M4
TCK
Test Clock (5 V Tolerant Input):
Provides the clock to
the JTAG test logic.
37
10
7
N4
TRST
Test Reset (3.3 V Input with internal pull-up):
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should
be pulsed low on power-up, or held low, to ensure that
the MT90823 is in the normal functional mode.
38
11
8
M5
IC
Internal Connection (3.3 V Input with internal pull-
down):
Connect to V
SS
for normal operation. This pin
must be low for the MT90823 to function normally and
to comply with IEEE 1149 (JTAG) boundary scan
requirements.
39
12
9
N5
RESET
Device Reset (5 V Tolerant Input):
This input (active
LOW) puts the MT90823 in its reset state to clear the
device internal counters, registers and bring STo0 - 15
and microport data outputs to a high impedance state.
The time constant for a power up reset circuit must be a
minimum of five times the rise time of the power supply.
In normal operation, the RESET pin must be held low
for a minimum of 100 nsec to reset the device.
40
13
10
M6
WFPS
Wide Frame Pulse Select (5 V Tolerant Input):
When
1, enables the wide frame pulse (WFP) Frame
Alignment interface. When 0, the device operates in
ST-BUS/GCI mode.
41 -
48
14-21
11 -
18
N6,M7,N7,N8,
M8,N9,M9,N10
A0 - A7
Address 0 - 7 (5 V Tolerant Input):
When non-
multiplexed CPU bus operation is selected, these lines
provide the A0 - A7 address lines to the internal
memories.
49
22
19
N11
DS/RD
Data Strobe / Read (5 V Tolerant Input):
For Motorola
multiplexed bus operation, this input is DS. This active
high DS input works in conjunction with CS to enable
the read and write operations.
For Motorola non-multiplexed CPU bus operation, this
input is DS. This active low input works in conjunction
with CS to enable the read and write operations.
For multiplexed bus operation, this input is RD. This
active low input sets the data bus lines (AD0-AD7, D8-
D15) as outputs.
Pin Description (continued)
Pin #
Name
Description
84
PLCC
100
MQFP
100
LQFP
120
BGA
相關(guān)PDF資料
PDF描述
MT90823AP 3V Large Digital Switch
MT90826 Quad Digital Switch
MT90826AG Quad Digital Switch
MT90826AL Quad Digital Switch
MT90826AL1 Quad Digital Switch
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90823AL1 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K/1K X 1K/512 X 512 3.3V 100MQFP - Trays 制造商:Microsemi Corporation 功能描述:PB FREE LOW VOLTAGE LARGE DIGITAL SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 2048X2048 100MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 2048X2048 100MQFP
MT90823AP 制造商:Microsemi Corporation 功能描述:
MT90823AP1 制造商:Microsemi Corporation 功能描述:LOW VOL LARGE DIGITAL SWCH
MT90826 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad Digital Switch
MT90826AG 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays
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