參數(shù)資料
型號: MT90823AL
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: 3V Large Digital Switch
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝: 14 X 20 MM, 2.80 MM HEIGHT, MO-112CC, MQFP-100
文件頁數(shù): 21/46頁
文件大小: 663K
代理商: MT90823AL
MT90823
Data Sheet
21
Zarlink Semiconductor Inc.
Table 12 - Offset Bits (OFn2, OFn1, OFn0, DLEn) and Frame Delay Bits (FD11, FD2-0)
Figure 5 - Examples for Input Offset Delay Timing
Input Stream
Offset
Measurement Result from
Frame Delay Bits
Corresponding
Offset Bits
FD11
FD2
FD1
FD0
OFn2
OFn1
OFn0
DLEn
No clock period shift (Default)
1
0
0
0
0
0
0
0
+ 0.5 clock period shift
0
0
0
0
0
0
0
1
+1.0 clock period shift
1
0
0
1
0
0
1
0
+1.5 clock period shift
0
0
0
1
0
0
1
1
+2.0 clock period shift
1
0
1
0
0
1
0
0
+2.5 clock period shift
0
0
1
0
0
1
0
1
+3.0 clock period shift
1
0
1
1
0
1
1
0
+3.5 clock period shift
0
0
1
1
0
1
1
1
+4.0 clock period shift
1
1
0
0
1
0
0
0
+4.5 clock period shift
0
1
0
0
1
0
0
1
ST-BUS F0i
CLK
STi Stream
STi Stream
STi Stream
STi Stream
GCI F0i
CLK
Input Stream
Input Stream
Input Stream
Input Stream
offset=0, DLE=0
offset=1, DLE=0
offset=0, DLE=1
offset=1, DLE=1
offset=0, DLE=0
offset=1, DLE=0
offset=0, DLE=1
offset=1, DLE=1
denotes the 3/4 point of the bit cell
Bit 7
Bit 7
Bit 7
Bit 7
Bit 0
Bit 0
Bit 0
Bit 0
denotes the 3/4 point of the bit cell
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