參數(shù)資料
型號： MT90812
廠商： Mitel Networks Corporation
英文描述： Integrated Digital Switch (IDX)(集成數(shù)字開關)
中文描述： 綜合數(shù)字交換機（IDX的）（集成數(shù)字開關）
文件頁數(shù)： 71/105頁
文件大小： 334K
代理商： MT90812
Advance Information
MT90812
67
22.22
D-Channel RX Control (DRXC)
The register is configured as follows:
The Enable bit for the RX FIFO is used to disable all the DBR circuitry including the transfer of data from DM to
the RX. If there is a read of the RX FIFO while it is disabled then the data is undefined.
In MLI mode, when the DBR is enabled the receiver identifies the first low bit as the start bit and then collects
bits as specified by the data rate, 1,2 or 8 bits per frame.
In FLI Mode when the ER bit is set the receiver transfers either 1,2 or 8 bits to the RX from Data Memory. If S=1
then the Start and Stop bits are expected on a per byte basis. If S=0 reception starts immediately after ER is
set.
Read/Write Address is: 41H
Reset Value is: 00
H
Bit
Name
Description
7
TXBO
Transmitter Bit Order
. When ‘0’ the first bit transmitted on the TDM channel is the
LSB read on the microport data bus (D0).
When ‘1’ The RX-FIFO will maintain the same bit ordering as an access to DM. That
is first bit transmitted in the TDM channel is the MSB read on the D7 of the microport
data bus.
6
RXBO
Receiver Bit Order
. When ‘0’ the first bit Received on the TDM channel is the LSB
read on the microport data bus (D0)
When ‘1’ the RX-FIFO will maintain the same bit ordering as an access to DM. That
is first bit received on the TDM channel is the MSB read on the D7 of the microport
data bus.
5-4
W1-W0
Data Rate
00 = 1 bit per frame
01 = 2 bits per frame
10= 8 bits per frame
3
M
1 = Message Length Interrupt Mode
, i.e. Message oriented, or Message oriented
with parity.
0 = FIFO Level Interrupt Mode
, i.e. Unframed, Byte oriented, or Byte oriented with
parity.
2
ER
Enable Receiver
. If 0, clears RX FIFO and resets counter. When ER=0, data is
undefined when a RX FIFO read is performed. ER= 1, the Receiver is enabled.
1
PE
Parity Enable
. In MLIM, if 0 the receiver does not expect the Parity bit. If 1 the
receiver expects the Parity bit following the message bits and before the stop bit.
In FLIM, when SE=1 and PE = 1 the receiver expects a parity bit per message
byte. Otherwise no parity bit is expected.
If parity is enabled then an even number of logic 1’s is expected in the data words
and parity bit.
0
SE
Start and Stop bit Enable
. In FLI mode, if SE=0 then no start and stop bits are
expected. If SE=1 then start and stop bits are expected in each message byte. In
MLI mode Start and Stop bits are always expected.
7
6
5
4
3
2
1
0
M
ER
SE
W1
W0
RXBO
PE
TXBO
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相關代理商/技術參數(shù)
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