參數(shù)資料
型號: MT90812
廠商: Mitel Networks Corporation
英文描述: Integrated Digital Switch (IDX)(集成數(shù)字開關)
中文描述: 綜合數(shù)字交換機(IDX的)(集成數(shù)字開關)
文件頁數(shù): 52/105頁
文件大?。?/td> 334K
代理商: MT90812
MT90812
Advance Information
48
For a continuous signal, such as dial tone, where there is no off time, an interrupt occurs when the counter
reaches a maximum count of 508 msec. When a maximum count of 508 msec is reached the P bit can be used
to determine if the interrupt was a result of a transition or a counter overflow. If the P bit remains unchanged
from its previous value then the interrupt is a result of a counter overflow.
Interrupts are generated with a minimum of 4 msec (32 frames) between consecutive IRQs. If a threshold is
crossed within 4 msec of the last interrupt, the interrupt will be held off and the SSCR will be updated after the
4 msec time has transpired. Refer to Fig. 27. For example, if the signal envelope crosses the threshold levels at
point B and point C, then there will be an interrupt generated at point D 32 frames from point A. The SSCR is
updated at the delayed IRQ point D with the last position and count, P=1 and t2, the time between points B to
C.
Figure 27 - Time Between Supervisory Signal Detection Interrupts
≥ 4
ms
Table 18 lists the registers which are used for the energy detect blocks.
Table 18 - Supervisory Signal Detection Registers
Refer to MSAN-178 note for Implementing an Algorithm for Interpreting The Measured Cadence of a Call
Progress Signal by the MT90812.
Register
Description
Page
EDA/B
Energy Detect
page 61
EDALT/EDAHT
Energy Detect A Low and High Threshold
page 62
EDBLT/EDBHT
Energy Detect B Low and High Threshold
page 63
SSCR1/2
Supervisory Signal Cadence Registers
page 62 and page 64
t1
t3
A, P=1, t0
E, P=0, t3
High threshold level
Low threshold level
Signal
Envelope
B
4ms
C
t2
D, P=1, t2
F, P=1, t4
t4
4ms
Interrupt
Delayed
interrupt
Interrupt
4ms
Interrupt
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相關代理商/技術參數(shù)
參數(shù)描述
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