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MT90500
89
SINGLE
3
R/W
Single Frame Assembly. When ‘1’, this bit indicates that cells must be assembled one
frame at a time, which allows an even cell flow. When it is ‘0’, it indicates that cells are
formed 4 frames at a time, which allows better external memory efficiency. This register
must not be changed when the scheduler is enabled. For full 1024 VC (or 1024 TDM time
slot) operation, this bit must be ‘0’.
Reserved
5:4
R/W
Reserved. These bits must always be written as “00”.
AAL5_INIT
7:6
W/O
Initialization bits for AAL5 operation. These two bits must be written, at initialization, in
all
three schedulers for AAL5 operation in
any
scheduler, regardless of how many schedulers
are active. The INIT pattern is different in each of the three schedulers:
2014h, Scheduler A(7:6): ‘01’
2024h, Scheduler B(7:6): ‘10’
2034h, Scheduler C(7:6): ‘11’
Reserved
15:8
R/O
Reserved. These bits must always be “0000_0000”.
Table 22 - TX_SAR Control Structure Base Address Register
Address: 2040 (Hex)
Label: TXCSBA
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
TXBASE
4:0
R/W
TX Control Structure Base Address. When accessing a Transmit Control Structure,
TXBASE represents address bits<20:16>; the address in the scheduler, bits<15:4>. This
register must not be changed when any scheduler is enabled.
Reserved
15:5
R/O
Reserved. Always read as “0000_0000_000”.
Table 23 - Transmit Data Cell FIFO Base Address Register
Address: 2050 (Hex)
Label: TXDFBA
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
TXFFBASE
11:0
R/W
Transmit Data Cell FIFO Base Address. Represents address bits<20:9> that point to the
first structure in the Transmit Data Cell FIFO. The lower bits of this pointer are
“0_0000_0000”. Each non-CBR cell occupies a 64-byte buffer. The Transmit Data Cell
FIFO must not overlap an 8 Kbyte boundary. When this register is changed, TXFFENA (in
the TX_SAR Control Register at 2000h) must not be asserted.
TXFFSIZ
13:12
R/W
Transmit Data Cell FIFO Size. This field indicates the number of non-CBR data cells in the
Transmit Data Cell FIFO. “00”=16 cells; “01”=32 cells; “10”=64 cells; “11”=128 cells. When
this register is changed, TXFFENA (in the TX_SAR Control Register at 2000h) must not be
asserted.
Reserved
15:14
R/W
Reserved. Always read as “00”.
Table 24 - Transmit Data Cell FIFO Write Pointer Register
Address: 2052 (Hex)
Label: TXDFWP
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
TXFFWP
7:0
R/W
Transmit Data Cell FIFO Write Pointer. Indicates cell structure number in which the CPU is
currently writing (the cell is not yet valid) within the Transmit Data Cell FIFO.
Reserved
15:8
R/O
Reserved. Always read as 00h.
Table 21 - TX_SAR End Ratio Register
Address: Scheduler A: 2014 (Hex); Scheduler B: 2024 (Hex); Scheduler C: 2034 (Hex)
Label: TESERA; TESERB; TESERC
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description