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參數資料
| 型號： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR(多通道 ATM AAL1分段及重組設備（基于通訊總線的系統(tǒng)與ATM網絡的接口）) |
| 中文描述： | 多通道自動柜員機AAL1特區(qū)（多通道自動柜員機AAL1分段及重組設備（基于通訊總線的系統(tǒng)與空中交通管理網絡的接口）） |
| 文件頁數： | 36/159頁 |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
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MT90500
36
4.1.4.2
External Memory to Internal Memory Control Structures
To know which internal frame buffer TDM channels need to be written (generally, only the TDM channels
scheduled for transmission on the TDM bus), the MT90500 uses control data from the External to Internal
Memory Control Structure. The External to Internal Memory Control Structure is located in external memory,
and is depicted in Figure 7. The control data in the External to Internal Memory Control Structure tells the
hardware where in external memory the receive data is located (Rx Circ. Buf. Address), the size of the Receive
Circular Buffer used, and to which TDM channel (TDM Channel #) this data must be written.
The External to Internal Memory Control Structure uses a 32-bit control word, as indicated below and in
Figure 7:
Bit<15> - V - Valid bit. If HIGH, indicates that this entry is valid, and the associated Receive Circular
Buffer is active. If an entry is not valid, it is simply bypassed and the next entry is read.
Bit<14> - D - Write-back Disable bit. If HIGH, the receive TDM data will be left unaltered in the Receive
Circular Buffer. If LOW, FFh will be written over each byte of the receive TDM data once it has been
transferred to the internal frame memory. (This has the effect of putting FFh - silence - on the TDM bus
if the Receive Circular Buffer underruns and the same byte is read again before new TDM output data is
written to the Receive Circular Buffer by the RX_SAR.)
Bit<13> - U - TDM read Underrun detection enable. If this bit is HIGH, and the External Memory to
Internal Memory Process tries to transfer a byte which has already been transferred, an underrun event
is detected and an interrupt may be generated. See registers 6000h, 6002h, 6046h and 6048h. This bit
(and TDM Read Underrun Detection circuit) work independently of the state of the ‘D’ bit. If this bit is
written low, TDM Read Underrun detection stops for this TDM channel on the present TDM frame.
Bits<12:11> - R - Not used.
Bits<10:0> - TDM Channel # - identifies a destination TDM channel number and stream
Bits<10:4> identify a TDM channel within a TDM stream. The channels are numbered from 0 to
127.
Bits<3:0> identify a TDM stream number, from 0 to 15 (corresponding to the ST[0:15] pins).
Rx Circ. Buff. Address and Size - indicates the Receive Circular Buffer address, and the size of the
Receive Circular Buffer (64, 128, 256, 512, or 1,024 bytes). The leading bits in the field, when appended
by a number of least-significant zeroes, indicate the Receive Circular Buffer address. The total number
of bits representing an address should be 21 bits. For example, for a 128-byte buffer, the 14-bit address
given in the structure will be appended by 7 zeroes, resulting in a 21-bit address.
It is important to consider this control structure when determining the location of Receive Circular Buffers in
external memory. Examining the configuration shown in Figure 7 on the next page, it can be seen that the
number of bits available to identify the address of Receive Circular Buffers differs depending on the size of the
buffer. Due to this restriction, it is essential that each buffer be located only on a boundary corresponding to the
size of the buffer (i.e. 64-byte buffers must be located on 64-byte boundaries, 128-byte buffers must be located
on 128-byte boundaries, and so on...).
Once all of the entries have been scanned, the internal frame memory is filled and the External Memory to
Internal Memory process terminates. If the process is still active four frames after being started, a “TDM Out of
Bandwidth Error” (found in the TDM Interface Status Register at 6002h) is generated.
The final step is for the MT90500 to drive the TDM data out on the TDM pins, ST[15:0]. Since not all time slots
are designated as outputs, separate Output Enable Registers located at addresses 7000 + 2N (N = 0, 1, ...,
127) are used for individual time slot output enable control. In addition, the GENOE bit in the TDM Interface
Control Register at 6000h must be set HIGH to enable the general Internal Memory to TDM Output Process
(see Section 4.1.2.3 for more details).
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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