參數(shù)資料
型號(hào): MT90220
廠商: Mitel Networks Corporation
英文描述: IC, MICREL LDO 5A ADJ VLT REG TO-2
中文描述: 八路IMA的/單向物理層設(shè)備
文件頁(yè)數(shù): 2/116頁(yè)
文件大小: 306K
代理商: MT90220
第1頁(yè)當(dāng)前第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)
MT90220
2
Applications
Cost effective single chip solution to implement
IMA and UNI links over T1 or E1 in all public or
private UNI, NNI and B-ICI applications
ATM Edge switch IMA and UNI Line Card
Design
Can be used for cost reduction in current
applications based on FPGA implementation
Description
The MT90220 device is targeted to systems
implementing the ATM FORUM UNI specifications for
T1/E1 rates or Inverse Multiplexing for ATM (IMA). In
the MT90220 architecture, up to 8 physical and
independent T1/E1 streams can be terminated
through the utilization of off-the-shelf, traditional T1/
E1 framers and LIUs. This allows ATM designers to
leverage
previous
T1/E1
hardware and software implementation, and to select
the best T1/E1 framer for the required application.
design
experience,
The MT90220 device provides ATM system
designers
with
a
flexible
implementing ATM access over existing and
deployed trunk interfaces, allowing a migration
towards ATM service technology. In addition to
allowing for the design of ATM UNI specifications for
T1/E1 rates, the MT90220 device is compliant with
the ATM FORUM IMA specifications for controlling
IMA groups of up to 8 trunks in a single chip. The
MT90220 can be configured to operate in different
modes to facilitate the implementation of the IMA
function at both CPE and Central Office sites. For
systems targeting ATM over T1/E1 with IMA and UNI
operating simultaneously, the MT90220 device
provides the ideal architecture and capabilities.
architecture
when
The device provides up to 4 internal IMA circuits and
allows for bandwidth scaleability through the use of
the UTOPIA MPHY, Level 2 specification at 25Mhz.
The implementation of the IMA as per AF-PHY-
0086.001 Inverse Multiplexing for ATM (IMA)
Specification Version 1.1 is divided into hardware
and software functions. Hardware functions are
implemented in the MT90220 device and software
functions are implemented by the user. Additional
hardware functions are included to assist in the
collection of statistical information to support MIB
implementation.
Hardware functions that are implemented in the
MT90220 device are:
Utopia Level 2 PHY Interface
Incoming HEC verification and correction
(optional),
Generation of a new HEC byte
Format outgoing bytes into multi-vendor PCM
formats
Retrieve ATM Cells from the incoming multi-
vendor PCM format
Perform cell delineation
Provide various counters to assist in
performance monitoring
Hardware functions that are implemented by the IMA
processor in the MT90220 device are:
Transmit scheduler (one per IMA group)
Generation of the TX IMA Data Cell Rate
Generation and insertion of ICP cells, Filler
Cells and Stuff Cells in IMA mode and Idle Cells
in UNI (non-IMA) mode; the ICP cells are
programmed by the user and the Filler and Idle
cells are pre-defined
Retrieve and process ICP cells in IMA Mode
Perform IMA Frame synchronization
Management of RX links to be part of the
internal re-sequencer when active
Extraction of RX IMA Data Cell Rate
Verification of delays between links
Perform re-sequencing of ATM cells using
external asynchronous Static RAM
Can accommodate more than 400 msec of link
differential delay depending on the amount of
external memory
Provide structured Interrupt scheme to report
various events.
相關(guān)PDF資料
PDF描述
MT90220AL Octal IMA/UNI PHY Device
MT90221 Quad IMA/UNI PHY Device
MT90221AL Quad IMA/UNI PHY Device
MT9041B T1/E1 System Synchronizer
MT9041BP T1/E1 System Synchronizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90220AL 制造商:Zarlink Semiconductor Inc 功能描述:I.C.
MT90220ALX01 制造商:Mitel Networks Corporation 功能描述:
MT90221 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device
MT90221AL 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device
MT90222 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device