參數(shù)資料
型號(hào)： MT8941BE
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Advanced T1/CEPT Digital Trunk PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PDIP24
封裝： PLASTIC, MS-011AA, DIP-24
文件頁(yè)數(shù)： 3/27頁(yè)
文件大?。?/td> 491K
代理商： MT8941BE
MT8941B
Data Sheet
3
Zarlink Semiconductor Inc.
11
13
C4o
Clock 4.096 MHz (Three state output)
- This is the inverse of the signal appearing on pin
13 (C4b) at 4.096 MHz and has a rising edge in the frame pulse (F0b) window. The high
impedance state of this output is controlled by ENC4o (pin 9).
12
14
V
SS
C4b
Ground (0 Volt)
13
15
Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output)
- When
the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the
falling edge in the frame pulse (F0b) window. When pin 17 is LOW, C4b is an input to an
external clock at 4.096 MHz.
14
16
C2o
Clock 2.048 MHz (Three state output)
- This is the divide by two output of C4b (pin 13) and
has a falling edge in the frame pulse (F0b) window. The high impedance state of this output
is controlled by EN
C2o
(pin 16).
Clock 2.048 MHz (Three state output) -
This is the divide by two output of C4b (pin 13) and
has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is
controlled by EN
C2o
(pin 16).
EN
C2o
Enable 2.048 MHz clock (TTL compatible input) -
This active high input enables both C2o
and C2o outputs (pins 14 and 15). When LOW, these outputs are in high impedance
condition.
15
17
C2o
16
19
17
20
MS3
Mode select 3 input (TTL compatible) -
This input in conjunction with MS2 (pin 7) selects
the minor mode of operation for DPLL #2. (Refer to Table 3.)
18,
19
21,
22
Ai, Bi
Inputs A and B (TTL compatible) -
These are the two inputs of the uncommitted NAND
gate
.
20
23
Y
o
CVb
Output Y (Totem pole output) -
Output of the uncommitted NAND gate.
21
24
Variable clock Bidirectional (TTL compatible input and Totem-pole output) -
When
acting as an output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the
1.544 MHz clock locked to the input frame pulse F0i (pin 5). When MS1 is HIGH, it is an
input to an external clock at 1.544 MHz or 2.048 MHz to provide the internal signal at 8 kHz
to DPLL #2.
22
26
CV
Variable clock (Three state output) -
This is the inverse output of the signal appearing on
pin 21, the high impedance state of which is controlled by EN
CV
(pin 1).
Reset (Schmitt trigger input)
- This input (active LOW) puts the MT8941B in its reset state.
To guarantee proper operation, the device must be reset after power-up. The time constant
for a power-up reset circuit (see Figures 9-13) must be a minimum of five times the rise time
of the power supply. In normal operation, the RST
pin must be held low for a minimum of
60 nsec to reset the device.
23
27
RST
24
28
V
DD
NC
V
DD
(+5 V)
Power supply.
No Connection.
4,
5,
18,
25
Pin Description (continued)
Pin #
Name
Description
DIP
PLCC
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