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參數(shù)資料
| 型號： | MT8941BE |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Advanced T1/CEPT Digital Trunk PLL |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDIP24 |
| 封裝： | PLASTIC, MS-011AA, DIP-24 |
| 文件頁數(shù)： | 10/27頁 |
| 文件大小： | 491K |
| 代理商： | MT8941BE |
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MT8941B
Data Sheet
10
Zarlink Semiconductor Inc.
The T1 and CEPT standards specify that, for free running equipment, the output clock tolerance must be less than
or equal to
±
32ppm and
±
50ppm respectively. This requirement restricts the oscillators of DPLL #1 and DPLL #2
to have maximum tolerances of
±
32ppm and
±
50ppm respectively.
Table 6 - Lock-in Range vs. Oscillator Frequency Tolerance
Figure 5 - The Spectrum of the Inherent Jitter for either PLL
Oscillator Clock*
Tolerance (
±
ppm)
Lock-in Range (
±
Hz)
DPLL #1
2.55
2.51
2.43
2.33
2.19
1.79
1.39
1.19
DPLL #2
1.91
1.87
1.79
1.69
1.55
1.15
.75
.55
5
10
20
32
50
100
150
175
Note: * Please refer to the section on “Jitter Performance and Lock-in
Range” for recommended oscillator tolerances for DPLL #1 & #2.
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PDF描述 |
|---|---|
| MT8941BP | Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP1 | Advanced T1/CEPT Digital Trunk PLL |
| MT8941BPR | Round Conductor Flat Cable, 3849/96 30 AWG, .033 (0.85) |
| MT8941BPR1 | Advanced T1/CEPT Digital Trunk PLL |
| MT8941 | CMOS ST-BUS⑩ FAMILY Advanced T1/CEPT Digital Trunk PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8941BP | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Advanced T1/CEPT Digital Trunk PLL |
| MT8941BP1 | 制造商:Microsemi Corporation 功能描述:ADVANCED T1/CEPT DIG TRUNK PLL EOL160209 |
| MT8941BPR | 制造商:ZARLINK 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT8941BPR1 | 制造商:Microsemi Corporation 功能描述:ADVANCED T1/CEPT DIG.TRUNK PLL EOL160209 |
| MT8950 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO-CMOS ST-BUS⑩ FAMILY Data Codec |
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