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參數(shù)資料
| 型號： | MT88EBNR |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | 4-Wire Calling Number Identification Circuit 2 (4-Wire CNIC2) |
| 中文描述： | TELEPHONE CALLING NO IDENT CKT, PDSO20 |
| 封裝： | 5.30 MM, MO-150AE, SSOP-20 |
| 文件頁數(shù)： | 24/30頁 |
| 文件大小： | 523K |
| 代理商： | MT88EBNR |
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MT88E45
Data Sheet
24
Zarlink Semiconductor Inc.
Figure 14 - 3-Wire FSK Data Interface Timing (Mode 1)
Figure 15 - Application Timing for Bellcore On-hook Data Transmission Associated with Ringing,
e.g., CID
Notes:
This on-hook case application is included because a CIDCW (off-hook) CPE must be also capable of receiving on-hook data
transmission (with ringing) from the end office.
1) PWDN and FSKen are internal signals decoded from CB0/1/2.
2) The CPE designer may choose to enable the MT88E45B only after the end of ringing to conserve power in a battery operated CPE.
CD is not activated by ringing.
3) The microcontroller in the CPE powers down the MT88E45B after CD has become inactive.
4) The microcontroller times out if CD is not activated.
5) This signal represents the mode of the DR/STD pin.
Demodulated Data
(Internal Signal)
DCLK (Data Clock)
(Schmitt Input)
DR (Data Ready)
(Output)
stop
start
stop
0
1
2
3
4
5
6
7
7
Word N
Word N+1
DATA
(Output)
5
Word N
Word N-1
1/f
DCLK1
t
RL
>t
DDH
The DCLK input must be low before and after DR falling edge.
Note 1: DCLK occurs during DR low and returns DR to high.
Note 2: DCLK occurs after DR, so DR is low for half a nominal bit time.
>t
DDS
4
3
2
1
0
6
7
stop
stop
7
0
Note 1
Note 2
1st Ring
2nd Ring
Ch. seizure
Mark
Data
A
C
D
E
F
..101010..
Data
Note 2
Note 3
Note 2
Note 4
t
CA
t
CP
B
TIP/RING
PWDN
Note 1
OSC2
FSKen
Note 1
CD
DR
Note 5
DCLK
DATA
A = 2sec typical
B = 250-500ms
C = 250ms
D = 150ms
E = feature specific
Max C+D+E = 2.9 to 3.7sec
F
≥
200ms
t
PD
t
PU
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