參數(shù)資料
型號: MT88EBNR
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 無繩電話/電話
英文描述: 4-Wire Calling Number Identification Circuit 2 (4-Wire CNIC2)
中文描述: TELEPHONE CALLING NO IDENT CKT, PDSO20
封裝: 5.30 MM, MO-150AE, SSOP-20
文件頁數(shù): 21/30頁
文件大?。?/td> 523K
代理商: MT88EBNR
MT88E45
Data Sheet
21
Zarlink Semiconductor Inc.
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
*Notes:
1. FSK input data at 1200
±
12 baud.
2. OSC1 at 3.579545 MHz
±
0.1%.
3. Function of signal condition.
AC Electrical Characteristics
- CAS Detection Timing
Characteristics
Sym.
Min.
Max.
Units
Notes
1
Tone present detect time
t
DP
t
DA
0.5
10
ms
See Figures16 16, 1717
2
Tone absent detect time
0.1
8
ms
See Figures16 16, 1717
AC Electrical Characteristics
- Oscillator and Carrier Detect Timing
Characteristics
Sym.
Min.
Max.
Units
Notes
1
OSC2
Power-up time
t
PU
t
PD
t
CP
50
ms
2
Power-down time
10
ms
3
CD
Input FSK to CD
low delay
25
ms
4
Input FSK to CD
high delay
t
CA
10
ms
5
Hysteresis
10
ms
AC Electrical Characteristics
- 3-Wire FSK Data Interface Timing (Mode 0)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes*
1
DR/STD
Rise time
t
RR
200
ns
into 50 pF Load
2
Fall time
t
RF
200
ns
into 50 pF Load
3
Low time
t
RL
415
416
417
μ
s
2
4
DATA
Rate
1188
1200
1212
baud
1
5
Input FSK to DATA
delay
t
IDD
1
5
ms
6
DATA
DCLK
Rise time
t
R
200
ns
into 50 pF Load
7
Fall time
t
F
200
ns
into 50 pF Load
8
DATA to DCLK delay
t
DCD
6
416
μ
s
1, 2, 3
9
DCLK to DATA delay
t
CDD
6
416
μ
s
1, 2, 3
10
DCLK
Frequency
f
DCLK0
t
CH
1201.6
1202.8
1204
Hz
2
11
High time
415
416
417
μ
s
2
12
Low time
t
CL
415
416
417
μ
s
2
13
DCLK
DR/STD
DCLK to DR delay
t
CRD
415
416
417
μ
s
2
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