
MT8843
5-39
sources on initial power up until there is sufficient
time to charge the capacitors.
It is possible to clear StD and its interrupt by
asserting PWDN immediately after system power up.
When PWDN is high, StD is low. PWDN will also
force both ESt and the comparator output low, Q2
will turn on so that the capacitor at the St/GT pin
charges up quickly (refer to Figure 4).
Power Down Mode
For
consumption, the CNIC2 can be powered up only
when it is required, that is, upon detection of one of
three CLIP/CID call arrival indicators: line reversal,
ring burst and ringing.
applications
requiring
reduced
power
The CNIC2 is powered down by asserting the PWDN
pin. In powerdown mode, the crystal oscillator,
opamp and all internal circuitry, except for TRIGin,
TRIGRC and TRIGout pins, are disabled. The three
TRIG pins are not affected by power down, such that,
the CNIC2 can still react to call arrival indicators.
CNIC2 can be powered up by grounding the PWDN
pin.
Crystal Oscillator
The MT8843 requires a 3.579545MHz crystal
oscillator as the master timing source.
Figure 8 - Common Crystal Connection
The crystal specification is as follows:
Frequency:
Frequency tolerance:
Resonance mode:
Load capacitance:
Maximum series resistance: 150 ohms
Maximum drive level (mW):
e.g., CTS MP036S
3.579545 MHz
±
0.1%(-40
o
C+85
o
C)
Parallel
18 pF
2 mW
Any number of MT8843 devices can be connected as
shown in Figure 8 such that only one crystal is
required. The connection between OSC2 and OSC1
can be D.C. coupled as shown, or the OSC1 input on
all devices can be driven from a CMOS buffer (dc
coupled) with the OSC2 outputs left unconnected.
To meet BT and Bellcore requirements for proper
tone detection the crystal must have a frequency
tolerance of 0.1%.
VRef and CAP Inputs
V
Ref
is the output of a low impedance voltage source
equal to V
DD/2
and is used to bias the input opamp. A
0.1
μ
F capacitor is required between CAP and V
SS
to
eliminate noise on V
Ref.
Applications
The circuit shown in Figure 9 illustrates the use of the
MT8843 (CNIC2) device in a proprieitary system that
doesn’t need to meet FCC, DOC, and UL approvals. It
should be noted that if glitches on the tip/ring interface
are of sufficient amplitude, the circuit will falsely detect
these signals as ringing or line reversal.
The circuit shown in Figure 10 will provide common
mode rejection of signals received by the ringing circuit.
This circuit should pass safety related tests specified by
FCC Part 68, DOC CS-03, UL 1459, and CSA C22.2.
These safety tests will simulate high voltage faults that
may occur on the line. The circuit provides isolation
from these high voltage faults via the 430k
, 12k1 re-
sistors and the 22nF & 330nF capacitors. The 430k
resistors are manufactured by IRC ( part number GS3).
These resistors are 3W, 5%, 1kV power resistors. The
12k1 resistor is manufactured by IRC (part number
FA8425F). This resistor is a 1.5W, 5%, fuseable type
resistor. The 22nF and 330nF capacitors have a 400V
rating.
Approvals
FCC Part 68, DOC CS-03, UL 1459 and CAN/CSA-
22.2 No. 225-M90 are all system (i.e., connectors,
power supply, cabinet, etc.) requirements. Since the
MT8843 is a component and not a system, it cannot
be approved as a stand alone part by these
standards bodies. However, when installed into a
properly designed system, the application circuit
(Figure 10) has been designed to meet the CO Trunk
Interface requirements of FCC, DOC, UL and CSA;
thus enabling the complete system to be approved
by these standards bodies.
OSC1
OSC2
OSC1
OSC2
OSC1
OSC2
3.579545 MHz
MT8843
MT8843
MT8843
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