參數(shù)資料
型號: MT8843
廠商: Mitel Networks Corporation
英文描述: Calling Number Identification Circuit(主叫識別電路(提供各種主叫線信息傳遞設(shè)備的接口))
中文描述: 主叫號碼識別電路(主叫識別電路(提供各種主叫線信息傳遞設(shè)備的接口))
文件頁數(shù): 15/26頁
文件大?。?/td> 178K
代理商: MT8843
MT8843
5-45
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
TTypical figures are at 25
o
C and are for design aid only, not guaranteed and not subject to production testing
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
o
C and are for design aid only, not guaranteed and not subject to production testing.
*Notes:
1. FSK input data at 1200
±
12 baud.
2. OSC1 at 3.579545 MHz
±
0.1%.
3. Function of signal condition.
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics
- 3-Wire Interface Timing
Characteristics
Sym
Min
Max
Units
Notes*
1
PWDN
OSC1
Power-up time
t
PU
t
PD
t
CP
t
CA
50
ms
2
Power-down time
1
ms
3
CD
Input FSK to CD low delay
25
ms
4
Input FSK to CD high delay
8
ms
5
Hysteresis
8
ms
AC Electrical Characteristics
- 3-Wire Interface Timing (Mode 0)
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
DR
Rise time
t
RR
t
RF
t
RL
200
ns
into 50pF Load
2
Fall time
200
ns
into 50pF Load
3
Low time
415
416
417
μ
s
2
4
DATA
Rate
1188
1200
1212
baud
1
5
Input FSK to DATA delay
t
IDD
t
R
t
F
t
DCD
t
CDD
f
DCLK0
t
CH
t
CL
t
CRD
1
5
ms
6
DATA
DCLK
Rise time
200
ns
into 50pF Load
7
Fall time
200
ns
into 50pF Load
8
DATA to DCLK delay
6
416
μ
s
μ
s
1, 2, 3
9
DCLK to DATA delay
6
416
1, 2, 3
10
DCLK
Frequency
1201.6
1202.8
1204
Hz
2
11
High time
415
416
417
μ
s
μ
s
μ
s
2
12
Low time
415
416
417
2
13
DCLK
DR
DCLK to DR delay
415
416
417
2
AC Electrical Characteristics
- 3-Wire Interface Timing (Mode 1)
Characteristics
Sym
Min
Max
Units
Notes
1
DCLK
Frequency
f
DCLK1
1
MHz
2
Duty cycle
30
70
%
3
Rise time
t
R1
t
DDS
t
DDH
20
ns
4
DCLK,
DR
DCLK low set up to DR
500
ns
5
DCLK low hold time after DR
500
ns
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