參數(shù)資料
型號： MT8843
廠商： Mitel Networks Corporation
英文描述： Calling Number Identification Circuit(主叫識別電路（提供各種主叫線信息傳遞設(shè)備的接口）)
中文描述： 主叫號碼識別電路（主叫識別電路（提供各種主叫線信息傳遞設(shè)備的接口））
文件頁數(shù)： 2/26頁
文件大小： 178K
代理商： MT8843
MT8843
5-32
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
IN+
Non-inverting Input
of the internal opamp.
2
IN-
Inverting Input
of the internal opamp.
3
GS
Gain Select (Output)
of internal opamp. It is recommended that the opamp be set to unity
gain. Refer to figure 7 for equation to calculate the closed loop opamp gain.
4
V
Ref
CAP
Reference Voltage (Output)
. Nominally V
DD
/2
. It is used to bias the input opamp.
Capacitor
. A 0.1
μ
F decoupling capacitor should be connected across this pin and V
SS
.
TRIGin
Trigger Input
. Schmitt trigger buffer input. Used for line reversal and ring detection.
5
6
7
TRIGRC
Trigger RC (Open Drain Output/Schmitt Input)
. Used to set the (RC) time interval from
TRIGin going low to TRIGout going high. An external resistor connected to V
DD
and
capacitor connected to V
SS
determines the duration of the (RC) time interval.
TRIGout
Trigger Out (CMOS Output).
Schmitt trigger buffer output. Used to indicate detection of
line reversal and/or ringing.
8
9
MODE
3-wire interface: Mode Select (CMOS Input)
. When low, selects interface mode 0.
When high, selects interface mode 1. See pin 16 (DCLK) description to understand how
MODE affects the DCLK pin.
10
OSCin
Oscillator Input
. A 3.579545MHz crystal should be connected between this pin and
OSCout. It may also be driven directly from an external clock source.
11
OSCout
Oscillator Output
. A 3.579545MHz crystal should be connected between this pin and
OSCin. When OSCin is driven by an external clock, this pin should be left open.
12
V
SS
IC
Power Supply Ground
.
13
Internal Connection
. Must be connected to V
SS
for normal operation.
Power Down (Schmitt Input)
. Active high. When high, the device consumes minimal
power by disabling all functionality except TRIGin, TRIGRC and TRIGout. Must be pulled
low, for device operation.
14
PWDN
15
FSKen
FSK Enable (CMOS Input)
. Must be high for FSK demodulation. This pin should be set
low to prevent the FSK demodulator from reacting to extraneous signals (such as speech,
alert signal and DTMF which are all in the same frequency band as FSK).
16
DCLK
3-wire Interface: Data Clock (CMOS Input/Output)
. In mode 0 (MODE pin low), this pin
is an output. In mode 1 (MODE pin high), this pin is an input.
17
DATA
3-wire Interface: Data (CMOS Output)
. Mode 0 data appears at the pin once
demodulated. Mode 1 data is shifted out on the rising edge of the microcontroller
supplied DCLK.
VDD
St/GT
ESt
StD
INT
CD
DR
DATA
DCLK
FSKen
PWDN
IC
IN+
IN-
GS
VRef
CAP
TRIGin
TRIGRC
TRIGout
MODE
OSCin
OSCout
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT8843AE 制造商:Mitel Networks Corporation 功能描述:TELEPHONE CALLING NO IDENT CKT, PDIP24
MT8843AS 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS Calling Number Identification Circuit 2 Preliminary Information
MT8860 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:DTMF DECODER
MT8860XC 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:DTMF DECODER
MT8860XE 制造商:Hitachi 功能描述:DTMF RECEIVER, 18 Pin, Plastic, DIP 制造商:Microsemi Corporation 功能描述:DTMF RECEIVER, 18 Pin, Plastic, DIP 制造商:Mitel Networks Corporation 功能描述:DTMF RECEIVER, 18 Pin, Plastic, DIP
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