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| 型號： | MT80C51C-12R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 85/109頁 |
| 文件大?。?/td> | 10824K |
| 代理商： | MT80C51C-12R |
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62
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
Figure 11-3. Output Compare Unit, Block Diagram
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal
and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering
synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The
synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-
free.
The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU
has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly.
11.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the
Force Output Compare (0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the timer, but the
OC0x pin will be updated as if a real Compare Match had occurred (the COM0x[1:0] bits settings define whether the
OC0x pin is set, cleared or toggled).
11.5.2 Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle,
even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without
triggering an interrupt when the Timer/Counter clock is enabled.
11.5.3 Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks
involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is
running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in
incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-
counting.
The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The
easiest way of setting the OC0x value is to use the Force Output Compare (0x) strobe bits in Normal mode. The OC0x
Registers keep their values even when changing between Waveform Generation modes.
OCFnx (Int.Req.)
8-BIT COMPARATOR
OCRnx
OCnx
DATA BUS
TCNTn
WGMn[2:0]
WAVEFORM GENERATOR
top
FOCn
COMnX[1:0]
bottom
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