- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25623 > MT80C51C-12R (TEMIC SEMICONDUCTORS) 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 PDF資料下載
參數(shù)資料
| 型號： | MT80C51C-12R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 59/109頁 |
| 文件大小： | 10824K |
| 代理商： | MT80C51C-12R |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當(dāng)前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁
39
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
Table 9-2.
Interrupt 0 Sense Control
9.3.2
GIMSK – General Interrupt Mask Register
Bits 7:6 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bit 5 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is
enabled. Any change on any enabled PCINT[11:8] pin will cause an interrupt. The corresponding interrupt of Pin Change
Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT[11:8] pins are enabled individually by the PCMSK1
Register.
Bit 4 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is
enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt of Pin Change
Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled individually by the PCMSK0
Register.
Bits 3:1 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the MCU Control Register (MCUCR) define whether the
external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an
interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is
executed from the INT0 Interrupt Vector.
ISC01
ISC00
Description
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
Bit
76543210
–
PCIE1
PCIE0
–
INT0
GIMSK
Read/Write
R
R/W
R
R/W
Initial Value
0
00000
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT80C51C-20R | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44 |
| MF280C51-36R | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| MQ80C52EXXX-16/883D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| MR80C32-16/883 | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| MC80C52TXXX-25SC | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT80C51FB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT80C51FB/B | 制造商:Intel 功能描述: |
| MT80GB | 制造商:Datak Corporation 功能描述: |
| MT80JSF1G72NDY-1G1F1A2 | 制造商:Micron Technology Inc 功能描述:8GB 1GX72 DDR3 SDRAM MODULE PBF DIMM 1.5V REGISTERED - Trays |
| MT80KSF1G72NDY-1G4F1A3 | 制造商:Micron Technology Inc 功能描述:8GB 1GX72 DDR3 SDRAM MODULE PBF DIMM 1.35V FULLY BUFFERED - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。