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參數(shù)資料
| 型號(hào)： | MT80C51C-12R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 107/109頁 |
| 文件大?。?/td> | 10824K |
| 代理商： | MT80C51C-12R |
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809
32117D–AVR-01/12
AT32UC3C
Figure 30-4. IISC Clocks Generation
30.6.7
Mono
When the Transmit Mono (TXMONO) in the Mode Register is set, data written to the left channel
is duplicated to the right output channel. In TDM mode with more than two channels, numbered
from 0, data written to the even-numbered channels is duplicated to the following odd-numbered
channel.
When the Receive Mono (RXMONO) in the Mode Register is set, data received from the left
channel is duplicated to the right channel. In TDM mode with more than two channels, num-
bered from 0, data received from the even-numbered channels is duplicated to the following
odd-numbered channel.
30.6.8
Holding Registers
The IISC user interface includes a Receive Holding Register (RHR) and a Transmit Holding
Register (THR). RHR and THR are used to access audio samples for all audio channels.
When a new data word is available in the RHR register, the Receive Ready bit (RXRDY) in the
Status Register (SR) is set. Reading the RHR register will clear this bit.
A receive overrun condition occurs if a new data word becomes available before the previous
data word has been read from the RHR register. Then, the Receive Overrun bit in the Status
Register will be set and bit i of the RXORCH field in the Status Register is set, where i is the cur-
rent receive channel number.
When the THR register is empty, the Transmit Ready bit (TXRDY) in the Status Register (SR) is
set. Writing into the THR register will clear this bit.
A transmit underrun condition occurs if a new data word needs to be transmitted before it has
been written to the THR register. Then, the Transmit Underrun bit in the Status Register will be
MR.MODE = SLAVE
Clock
divider
MR.DATALENGTH
GCLK_IISC
Clock
enable
Clock
divider
CR.CKEN/CKDIS
MR.IMCKMODE
MR.DATALENGTH
MR.IMCKFS
MR.IMCKMODE
1
0
IMCK pin output
Clock
enable
CR.CKEN/CKDIS
Internal
bit clock
ISCK pin input
1
0
ISCK pin output
Internal
word clock
IWS pin input
1
0
IWS pin output
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