參數(shù)資料
型號(hào)： MT5C1009
廠商： Electronic Theatre Controls, Inc.
英文描述： 128K x 8 SRAM WITH CHIP & OUTPUT ENABLE
中文描述： 128K的× 8的SRAM在芯片
文件頁(yè)數(shù)： 1/17頁(yè)
文件大小： 254K
代理商： MT5C1009
SRAM
MT5C1009
Austin Semiconductor, Inc.
MT5C1009
Rev. 5.5 8/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
Access Times: 15, 20, 25, 35, 45, 55 and 70 ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power CMOS process
Single +5V (+10%) Power Supply
Easy memory expansion with CE\ and OE\ options.
All inputs and outputs are TTL compatible
OPTIONS
Timing
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-15
-20
-25
-35
-45
-55*
-70*
Package(s)
Ceramic DIP (400 mil)
Ceramic DIP (600 mil)
Ceramic LCC
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
Ceramic SOJ
C
CW
EC
ECA
F
DCJ
SOJ
No. 111
No. 112
No. 207
No. 208
No. 303
No. 501
No. 507
2V data retention/low power
L
*Electrical characteristics identical to those provided for the 45ns
access devices.
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
SMD 5962-89598
MIL-STD-883
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
V
SS
16
1
2
3
4
5
6
7
8
9
32 V
CC
31 A15
30 CE2
29 WE\
28 A13
27 A8
26 A9
25 A11
24 OE\
23 A10
22 CE\
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
32-Pin DIP (C, CW)
32-Pin SOJ (SOJ)
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
32-Pin Flat Pack (F)
32-Pin LCC (ECA)
GENERAL DESCRIPTION
The MT5C1009 is a 1,048,576-bit high-speed CMOS
static RAM organized as 131,072 words by 8 bits. This device
uses 8 common input and output lines and has an output en-
able pin which operate faster than address access times during
READ cycle.
For design flexibility in high-speed memory
applications, this device offers chip enable (CE\) and output
enable (OE\) features. These enhancements can place the out-
puts in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accom-
plished when WE\ remains HIGH and CE\ and OE\ go LOW.
The devices offer a reduced power standby mode when dis-
abled, allowing system designs to achieve low standby power
requirements.
The “L” version offers a 2V data retention mode, re-
ducing current consumption to 2mW maximum.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible. It is par-
ticularly well suited for use in high-density, high-speed system
applications.
128K x 8 SRAM
WITH CHIP & OUTPUT ENABLE
For more products and information
please visit our web site at
www.austinsemiconductor.com
4 3 2 1 32 31 30
A
A
A
N
V
C
A
C
N
14 15 16 17 18 19 20
D
D
V
S
D
D
D
D
5
6
7
8
9
10
11
12
13
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
29
28
27
26
25
24
23
22
21
WE
A13
A8
A9
A11
OE
A10
CE1
DQ8
\
\
\
6
NC
NC
NC
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