
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03
28
2003 Micron Technology, Inc.
Table 22:
Identification Register Definitions
INSTRUCTION FIELD
BIT
CONFIGURATION DESCRIPTION
Revision Number
(31:28)
0000
Reserved for version number.
Device Depth
(27:23)
00111
00110
Defines depth of 1Mb.
Degines depth of 512K.
Device Width
(22:18)
00011
00100
Defines width of x18 bits.
Defines width of x32 or x36 bits.
Micron Device ID
(17:12)
xxxxxx
Reserved for future use.
Micron JEDEC ID Code
(11:1)
00000101100
Allows unique identification of SRAM vendor.
ID Register Presence
Indicator (0)
1
Indicates the presence of an ID register.
Table 23:
Scan Register Sizes
REGISTER NAME
BIT SIZE
Instruction
3
Bypass
1
ID
32
Boundary Scan: x18, x32, x36
75
Table 24:
Instruction Codes
INSTRUCTION
CODE
DESCRIPTION
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.