
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03
22
2003 Micron Technology, Inc.
3.3V VDD, 3.3V I/O AC Test Conditions
Input pulse levels ....................VIH = (VDD/2.2) + 1.5V
................................................... VIL = (VDD/2.2) - 1.5V
Input rise and fall times......................................... 1ns
Input timing reference levels ........................ VDD/2.2
Output reference levels................................VDDQ/2.2
Output load .............................. See Figures 11 and 12
3.3V VDD, 2.5V I/O AC Test Conditions
Input pulse levels ................VIH = (VDD/2.64) + 1.25V
............................................... VIL = (VDD/2.64) - 1.25V
Input rise and fall times......................................... 1ns
Input timing reference levels ...................... VDD/2.64
Output reference levels...................................VDDQ/2
Output load .............................. See Figures
13 and
143.3V I/O Output Load Equivalents
Figure 11:
Figure 12:
2.5V VDD, 2.5V I/O AC Test Conditions
Input pulse levels .................... VIH = (VDD/2) + 1.25V
.................................................... VIL = (VDD/2) - 1.25V
Input rise and fall times......................................... 1ns
Input timing reference levels ........................... VDD/2
Output reference levels.................................. VDDQ/2
Output load............................... See Figures
13 and
142.5V I/O Output Load Equivalents
Figure 13:
Figure 14:
NOTE:
For Figures
11 and
13, 30pF = distributive test jig capacitance.
Q
VT = VDDQ/2.2
30pF
Z = 50
O
50
Q
351
317
5pF
+3.3V
Q
VT = VDDQ/2
30pF
Z = 50
O
50
Q
225
225
5pF
+2.5V