參數(shù)資料
型號(hào)： MT58L64V36PF-10
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 64K X 36 STANDARD SRAM, 5 ns, PBGA165
封裝： FBGA-165
文件頁(yè)數(shù)： 9/25頁(yè)
文件大?。?/td> 647K
代理商： MT58L64V36PF-10
17
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_2.p65 – Rev. 8/00
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (0°C
≤ T
A ≤ +70°C; VDD = +3.3V +0.3V/-0.165V)
-5
-6
-7.5
-10
DESCRIPTION
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX UNITS NOTES
Clock
Clock cycle time
tKC
5.0
6.0
7.5
10
ns
Clock frequency
fKF
200
166
133
100
MHz
Clock HIGH time
tKH
1.6
1.7
1.9
3.2
ns
2
Clock LOW time
tKL
1.6
1.7
1.9
3.2
ns
2
Output Times
Clock to output valid
tKQ
3.5
4.0
5.0
ns
Clock to output invalid
tKQX
1.0
1.5
ns
3
Clock to output in Low-Z
tKQLZ
0
1.5
ns
3, 4, 5, 6
Clock to output in High-Z
tKQHZ
3.5
4.0
5.0
ns
3, 4, 5, 6
OE# to output valid
tOEQ
3.5
4.0
5.0
ns
7
OE# to output in Low-Z
tOELZ
0000
ns
3, 4, 5, 6
OE# to output in High-Z
tOEHZ
3.0
3.5
4.0
4.5
ns
3, 4, 5, 6
Setup Times
Address
tAS
1.5
2.2
ns
8, 9
Address status (ADSC#, ADSP#)
tADSS
1.5
2.2
ns
8, 9
Address advance (ADV#)
tAAS
1.5
2.2
ns
8, 9
Write signals
tWS
1.5
2.2
ns
8, 9
(BWa#-BWd#, BWE#, GW#)
Data-in
tDS
1.5
2.2
ns
8, 9
Chip enables (CE#, CE2#, CE2)
tCES
1.5
2.2
ns
8, 9
Hold Times
Address
tAH
0.5
ns
8, 9
Address status (ADSC#, ADSP#)
tADSH
0.5
ns
8, 9
Address advance (ADV#)
tAAH
0.5
ns
8, 9
Write signals
tWH
0.5
ns
8, 9
(BWa#-BWd#, BWE#, GW#)
Data-in
tDH
0.5
ns
8, 9
Chip enables (CE#, CE2#, CE2)
tCEH
0.5
ns
8, 9
NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V +0.3V/-0.165V) and
Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V) unless otherwise noted.
2. Measured as HIGH above VIH and LOW below VIL.
3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
4. This parameter is sampled.
5. Transition is measured ±500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough
discussion on these parameters.
7. OE# is a “Don’t Care” when a byte write enable is sampled LOW.
8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times.
A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the required setup
and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
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