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參數(shù)資料
| 型號： | MT58L64V36PF-10 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 64K X 36 STANDARD SRAM, 5 ns, PBGA165 |
| 封裝： | FBGA-165 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 647K |
| 代理商： | MT58L64V36PF-10 |
22
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_2.p65 – Rev. 8/00
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
READ/WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A2
tCEH
tCES
BWE#,
BWa#-BWd#
(NOTE 4)
Q
High-Z
ADV#
Single WRITE
D(A3)
A4
A5
A6
D(A5)
D(A6)
D
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A1)
Q(A4)
Q(A4+1)
Q(A4+2)
tWH
tWS
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
(NOTE 1)
tKQLZ
tKQ
Back-to-Back
WRITEs
A1
(NOTE 5)
DON’T CARE
UNDEFINED
A3
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
tADSS
1.5
2.2
ns
tWS
1.5
2.2
ns
tDS
1.5
2.2
ns
tCES
1.5
2.2
ns
tAH
0.5
ns
tADSH
0.5
ns
tWH
0.5
ns
tDH
0.5
ns
tCEH
0.5
ns
-5
-6
-7.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
READ/WRITE TIMING PARAMETERS
-5
-6
-7.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
tKC
5.0
6.0
7.5
10
ns
fKF
200
166
133
100
MHz
tKH
1.6
1.7
1.9
3.2
ns
tKL
1.6
1.7
1.9
3.2
ns
tKQ
3.5
4.0
5.0
ns
tKQLZ
0
1.5
ns
tOELZ
0000
ns
tOEHZ
3.0
3.5
4.0
4.5
ns
tAS
1.5
2.2
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L64V36PT-5 | 制造商:Micron Technology Inc 功能描述: |
| MT58L64V36PT-7.5 | 制造商:Micron Technology Inc 功能描述: |
| MT58LC128K18B4LG-8.5 | 制造商:Cypress Semiconductor 功能描述:128KX18 SRAM PLASTIC TQFP 3.3V |
| MT58LC128K18C6LG-7.5 | 制造商:Cypress Semiconductor 功能描述:EOL, REPLACE WITH MT58L128L18D |
| MT58LC128K18D9LG-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM |
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