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參數(shù)資料
| 型號(hào)： | MT58L32L36P |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 32K x 36, 3.3V I/O, Pipelined, SCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器) |
| 中文描述： | 32K的× 36，3.3V的I / O的流水線，SCD的SyncBurst的SRAM（1兆，3.3V的輸入/輸出，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 16/17頁(yè) |
| 文件大?。?/td> | 329K |
| 代理商： | MT58L32L36P |
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1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, SCD SyncBurst SRAM
MT58L64L18P.p65 – Rev. 9/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
16
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, PIPELINED, SCD SYNCBURST SRAM
READ/WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A2
tCEH
tCES
BWE#,
BWa#-BWd#
(NOTE 4)
Q
High-Z
ADV#
Single WRITE
D(A3)
A4
A5
A6
D(A5)
D(A6)
D
BURST READ
Back-to-Back READs
(NOTE 5)
High-Z
Q(A2)
Q(A1)
Q(A4)
Q(A4+1)
Q(A4+2)
tWH
tWS
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
(NOTE 1)
tKQLZ
tKQ
Back-to-Back
WRITEs
A1
DON’T CARE
UNDEFINED
A3
NOTE:
1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
t
ADSS
t
WS
t
DS
t
CES
t
AH
t
ADSH
t
WH
t
DH
t
CEH
1.7
1.7
1.7
1.7
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
2.2
2.2
2.2
2.2
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
READ/WRITE TIMING PARAMETERS
-6
-7.5
-10
SYMBOL MIN
t
KC
f
KF
t
KH
t
KL
t
KQ
t
KQLZ
t
OELZ
t
OEHZ
t
AS
MAX
MIN
7.5
MAX
MIN
10
MAX
UNITS
ns
MHz
ns
ns
ns
ns
ns
ns
ns
6.0
166
133
100
1.7
1.7
1.9
1.9
3.2
3.2
3.5
4.2
5.0
1.5
0
1.5
0
1.5
0
3.5
4.2
4.5
1.7
2.0
2.2
-6
-7.5
-10
SYMBOL MIN
MAX
MIN
MAX
MIN
MAX
UNITS
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