
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM
MT58L64L18D.p65 – Rev. 9/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
3
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, PIPELINED, DCD SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
pins are only available on the x18 and x36 versions.
The device incorporates an additional pipelined
enable register which delays turning off the output
buffer an additional cycle when a deselect is executed.
This feature allows depth expansion without penaliz-
ing system performance.
Micron’s 1Mb SyncBurst SRAMs operate from a
+3.3V power supply, and all inputs and outputs are
TTL-compatible. The device is ideally suited for
Pentium
and PowerPC pipelined systems and systems
that benefit from a very wide, high-speed data bus. The
device is also ideal in generic 16-, 18-, 32-, 36-, 64- and
Please to (www.micron.com/mti/msp/html/sramprod.html
) for
the latest data sheet.
W eb * Pins 49 and 50 are reserved for address expansion.**No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.