參數(shù)資料
型號： MT55L64L36P1
廠商： Micron Technology, Inc.
英文描述： 64K x 36, 3.3V I/O, ZBT SRAM( 2Mb,3.3V輸入/輸出，靜態(tài)RAM)
中文描述： 64K的× 36，3.3V的I / O的ZBT SRAM的（處理器，3.3V的輸入/輸出，靜態(tài)內(nèi)存）
文件頁數(shù)： 8/23頁
文件大?。?/td> 404K
代理商： MT55L64L36P1
8
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM
MT55L128L18P1_2.p65
–
Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, PIPELINED ZBT SRAM
FBGA PIN DESCRIPTIONS
x18
6R
6P
x32/x36
6R
6P
2A, 2B, 3P,
3R, 4P, 4R,
8P, 8R, 9P,
9R, 10A, 10B
10P, 10R
5B
5A
4A
4B
SYMBOL
SA0
SA1
SA
TYPE
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
2A, 2B, 3P,
3R, 4P, 4R,
8P, 8R, 9P,
9R, 10A, 10B
10P, 10R, 11A
5B
4A
–
–
BWa#
BWb#
BWc#
BWd#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For
the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#
controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
controls DQds and DQPd. Parity is only available on the x18 and x36
versions.
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock
’
s rising
edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device. CE# is sampled only when a new external address is
loaded.
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Synchronous Clock Enable: This active LOW input permits CLK to
propagate throughout the device. When CKE# is HIGH, the device
ignores the CLK input and effectively internally extends the
previous CLK cycle. This input must meet setup and hold times
around the rising edge of CLK.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
Read/Write: This input determines the cycle type when ADV/LD# is
LOW and is the only means for determining READs and WRITEs.
READ cycles may not be converted into WRITEs (and vice versa)
other than by loading a new address. A LOW on this pin permits
BYTE WRITE operations and must meet the setup and hold times
around the rising edge of CLK. Full bus-width WRITEs occur if all
byte write enables are LOW.
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
6B
6B
CLK
Input
3A
3A
CE#
Input
6A
6A
CE2#
Input
7A
7A
CKE#
Input
11H
11H
ZZ
Input
7B
7B
R/W#
Input
3B
3B
CE2
Input
(continued on next page)
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