參數(shù)資料
型號(hào)： MT55L1MY18P
廠商： Micron Technology, Inc.
英文描述： 16Mb: 1 Meg x 18, Flow-Through ZBT SRAM(16Mb流通式同步靜態(tài)存儲(chǔ)器)
中文描述： 16Mb的：1梅格× 18，流量通過(guò)ZBT SRAM的（16Mb的流通式同步靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 9/34頁(yè)
文件大?。?/td> 460K
代理商： MT55L1MY18P
9
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1M18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
FBGA PIN DESCRIPTIONS
x18
6R
6P
x32/x36
6R
6P
2A, 9A, 10A,
2B, 9B, 10B,
3P, 4P, 8P,
9P, 10P, 3R,
4R, 8R, 9R,
10R, 11R
5B
5A
4A
4B
SYMBOL
SA0
SA1
SA
TYPE
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and
must meet the setup and hold times around the rising edge of
CLK.
2A, 9A, 10A,
11A, 2B, 9B,
10B, 3P, 4P,
8P, 9P, 10P,
3R, 4R, 8R,
9R, 10R, 11R
5B
4A
–
–
BWa#
BWb#
BWc#
BWd#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb.
For the x32 and x36 versions, BWa# controls DQas and DQPa;
BWb# controls DQbs and DQPb; BWc# controls DQcs and DQPc;
BWd# controls DQds and DQPd. Parity is only available on the
x18 and x36 versions.
Synchronous Clock Enable: This active LOW input permits CLK to
propogate throughout the device. When CKE# is HIGH, the
device ignores the CLK input and effectively internally extends
the previous CLK cycle. This input must meet the setup and hold
times around the rising edge of CLK.
Read/Write: This input determines the cycle type when ADV/LD#
is LOW and is the only means for determining READs and
WRITEs. READ cycles may not be converted into WRITEs (and vice
versa) other than by loading a new address. A LOW on this pin
permits BYTE WRITE operations to meet the setup and hold times
around the rising edge of CLK. Full bus-width WRITEs occur if all
byte write enables are LOW.
Clock: This signal registers the address, data, chip enable, byte
write enables and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is
sampled only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in
the memory array is retained. When ZZ is active, all other inputs
are ignored.
Synchronous Chip Enable: This active HIGH input is used to
enable the device and is sampled only when a new external
address is loaded.
7A
7A
CKE#
Input
7B
7B
R/W#
Input
6B
6B
CLK
Input
3A
3A
CE#
Input
6A
6A
CE2#
Input
11H
11H
ZZ
Input
3B
3B
CE2
Input
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相關(guān)PDF資料
PDF描述
MT55V1MV18P 16Mb: 1 Meg x 18, Flow-Through ZBT SRAM(16Mb流通式同步靜態(tài)存儲(chǔ)器)
MT55L512L18F 8Mb: 512K x 18,Flow-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲(chǔ)器)
MT55L256L32F 8Mb: 256K x 32，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲(chǔ)器)
MT55L256L36F 8Mb: 256K x 36，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲(chǔ)器)
MT55L256V32F 8Mb: 256K x 32，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲(chǔ)器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT55L1MY18PT-10 制造商:Cypress Semiconductor 功能描述:1MX18 SRAM PLASTIC TQFP 3.3V P
MT55L1MY18PT-6 制造商:Cypress Semiconductor 功能描述:1MX18 SRAM PLASTIC TQFP 3.3V P 制造商:Rochester Electronics LLC 功能描述:- Bulk
MT55L256L18F1F-10 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:
MT55L256L18F1T-11 制造商:Rochester Electronics LLC 功能描述:- Bulk
MT55L256L18F1T-12 制造商:Cypress Semiconductor 功能描述:256KX18 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk
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