- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385640 > MT55L1MY18P (Micron Technology, Inc.) 16Mb: 1 Meg x 18, Flow-Through ZBT SRAM(16Mb流通式同步靜態(tài)存儲器) PDF資料下載
參數(shù)資料
| 型號： | MT55L1MY18P |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 16Mb: 1 Meg x 18, Flow-Through ZBT SRAM(16Mb流通式同步靜態(tài)存儲器) |
| 中文描述： | 16Mb的：1梅格× 18，流量通過ZBT SRAM的（16Mb的流通式同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 26/34頁 |
| 文件大小： | 460K |
| 代理商： | MT55L1MY18P |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
26
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1M18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
IDCODE
The IDCODE instruction causes a vendor-specific,
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI and
TDO pins and allows the IDCODE to be shifted out of
the device when the TAP controller enters the Shift-DR
state. The IDCODE instruction is loaded into the in-
struction register upon power-up or whenever the TAP
controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also
places all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruc-
tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded
into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bi-directional pins is captured in the boundary
scan register.
The user must be aware that the TAP controller clock
can only operate at a frequency up to 10 MHz, while the
SRAM clock operates more than an order of magnitude
faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR
state, an input or output will undergo a transition. The
TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but
there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will
capture the correct value of a signal, the SRAM signal
must be stabilized long enough to meet the TAP
controller’s capture setup plus hold time (
t
CS plus
t
CH).
The SRAM clock input might not be captured correctly
if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in
the boundary scan register.
Once the data is captured, it is possible to shift out
the data by putting the TAP into the Shift-DR state. This
places the boundary scan register between the TDI and
TDO pins.
Note that since the PRELOAD part of the command
is not implemented, putting the TAP to the Update-DR
state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
IDENTIFICATION (ID) REGISTER
The ID register is loaded with a vendor-specific, 32-
bit code during the Capture-DR state when the IDCODE
command is loaded in the instruction register. The
IDCODE is hardwired into the SRAM and can be shifted
out when the TAP controller is in the Shift-DR state.
The ID register has a vendor code and other informa-
tion described in the Identification Register Definitions
table.
TAP INSTRUCTION SET
OVERVIEW
Eight different instructions are possible with the
three-bit instruction register. All combinations are listed
in the Instruction Codes table. Three of these instruc-
tions are listed as RESERVED and should not be used.
The other five instructions are described in detail be-
low.
The TAP controller used in this SRAM is not fully
compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully imple-
mented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
implement the 1149.1 commands EX TEST or INTEST or
the PRELOAD portion of SAMPLE/PRELOAD; rather it
performs a capture of the I/O ring when these instruc-
tions are executed.
Instructions are loaded into the TAP controller dur-
ing the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state, in-
structions are shifted through the instruction register
through the TDI and TDO pins. To execute the instruc-
tion once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
EXTEST
EX TEST is a mandatory 1149.1 instruction which is
to be executed whenever the instruction register is
loaded with all 0s. EX TEST is not implemented in this
SRAM TAP controller, and therefore this device is not
compliant to 1149.1.
The TAP controller does recognize an all-0 instruc-
tion. When an EX TEST instruction is loaded into the
instruction register, the SRAM responds as if a SAMPLE/
PRELOAD instruction has been loaded. There is one
difference between the two instructions. Unlike the
SAMPLE/PRELOAD instruction, EX TEST places the
SRAM outputs in a High-Z state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT55V1MV18P | 16Mb: 1 Meg x 18, Flow-Through ZBT SRAM(16Mb流通式同步靜態(tài)存儲器) |
| MT55L512L18F | 8Mb: 512K x 18,Flow-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器) |
| MT55L256L32F | 8Mb: 256K x 32，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器) |
| MT55L256L36F | 8Mb: 256K x 36，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器) |
| MT55L256V32F | 8Mb: 256K x 32，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L1MY18PT-10 | 制造商:Cypress Semiconductor 功能描述:1MX18 SRAM PLASTIC TQFP 3.3V P |
| MT55L1MY18PT-6 | 制造商:Cypress Semiconductor 功能描述:1MX18 SRAM PLASTIC TQFP 3.3V P 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L256L18F1F-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT55L256L18F1T-11 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L256L18F1T-12 | 制造商:Cypress Semiconductor 功能描述:256KX18 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。