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參數(shù)資料
| 型號： | MT55L1MY18P |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 16Mb: 1 Meg x 18, Flow-Through ZBT SRAM(16Mb流通式同步靜態(tài)存儲器) |
| 中文描述： | 16Mb的：1梅格× 18，流量通過ZBT SRAM的（16Mb的流通式同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 10/34頁 |
| 文件大小： | 460K |
| 代理商： | MT55L1MY18P |
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10
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1M18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
x18
8B
x32/x36
8B
SYMBOL
OE#
(G#)
ADV/LD#
TYPE
Input
DESCRIPTION
Output Enable: This
active LOW, asynchronous input enables the
data I/O output drivers.
Synchronous Address Advance/Load: When HIGH, this input is used
to advance the internal burst counter, controlling burst access after
the external address is loaded. When ADV/LD# is HIGH, R/W# is
ignored. A LOW on ADV/LD# clocks a new address at the CLK rising
edge.
Mode: This input selects the burst sequence. A LOW on this input
selects “l(fā)inear burst.” NC or HIGH on this input selects “interleaved
burst.” Do not alter input state while device is operating.
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated with
Output DQas; Byte “b” is associated with DQbs. For the x32 and x36
versions, Byte “a” is associated with DQas; Byte “b” is associated
with DQbs; Byte “c” is associated with DQcs; Byte “d” is associated
with DQds. Input data must meet setup and hold times around the
rising edge of CLK.
8A
8A
Input
1R
1R
MODE
(LBO#)
Input
(a)
10J, 10K,
10L, 10M, 11D 10L, 10M, 11J,
11E, 11F, 11G 11K, 11L, 11M
(b)
2D, 2E, 2F,
(b)
10D, 10E,
2G, 1J, 1K,
1L, 1M
(a)
10J, 10K,
DQa
DQb
10F, 10G, 11D,
11E, 11F, 11G
(c)
1D, 1E, 1F,
1G, 2D, 2E,
2F, 2G,
(d)
1J, 1K, 1L,
1M, 2J, 2K,
2L, 2M
11N
11C
1C
1N
1H, 2H, 4D,
DQc
DQd
11C
1N
–
–
NC/
DQPa
NC/
DQPb
NC/
DQPc
NC/
DQPd
V
DD
NC/
I/O
No Connect/Parity Data I/Os: On the x32 version, these are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
Supply Power Supply:
See DC Electrical Characteristics and Operating
Conditions for range.
1H, 2H, 4D,
4E, 4F, 4G, 4H, 4E, 4F, 4G, 4H,
4J, 4K, 4L, 4M, 4J, 4K, 4L, 4M,
7N, 8D, 8E, 8F, 7N, 8D, 8E, 8F,
8G,8H, 8J,
8K, 8L, 8M
3C, 3D, 3E, 3F, 3C, 3D, 3E, 3F,
3G, 3J, 3K, 3L, 3G, 3J, 3K, 3L,
3M, 3N, 9C,
9D, 9E, 9F,
9G, 9J, 9K,
9L, 9M, 9N
8G,8H, 8J,
8K, 8L, 8M
V
DD
Q
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Operating Conditions for range.
3M, 3N, 9C,
9D, 9E, 9F,
9G, 9J, 9K,
9L, 9M, 9N
FBGA PIN DESCRIPTIONS (continued)
(continued on next page)
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| MT55L256L18F1F-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
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