參數(shù)資料
型號： MT55L128V32F1T-11
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 128K X 32 ZBT SRAM, 8.5 ns, PQFP100
封裝： PLASTIC, MS-026, TQFP-100
文件頁數(shù)： 6/26頁
文件大?。?/td> 372K
代理商： MT55L128V32F1T-11
14
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18F1_F.p65 – Rev. F, Pub. 1/03 EN
2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
TRUTH TABLE
(Notes 5-10)
OPERATION
ADDRESS CE# CE2# CE2 ZZ ADV/ R/W# B W x OE# CKE# C L K
D Q
NOTES
USED
L D #
DESELECT Cycle
None
H
X
L
X
L
→H High-Z
DESELECT Cycle
None
X
H
X
L
X
L
→H High-Z
DESELECT Cycle
None
X
L
X
L
→H High-Z
CONTINUE DESELECT Cycle
None
X
L
H
X
L
→H High-Z
1
READ Cycle
External
L
H
L
H
X
L
→HQ
(Begin Burst)
READ Cycle
Next
X
L
H
X
L
→H
Q
1, 11
(Continue Burst)
NOP/DUMMYREAD
External
L
H
L
H
X
H
L
→H High-Z
2
(Begin Burst)
DUMMYREAD
Next
X
L
H
X
H
L
→H High-Z
1, 2,
(Continue Burst)
11
WRITE Cycle
External
L
H
L
X
L
→HD
3
(Begin Burst)
WRITE Cycle
Next
X
L
H
X
L
X
L
→H
D
1, 3,
(Continue Burst)
11
NOP/WRITE ABORT
None
L
H
L
H
X
L
→H High-Z
2, 3
(Begin Burst)
WRITE ABORT
Next
X
L
H
X
H
X
L
→H High-Z
1, 2,
(Continue Burst)
3, 11
IGNORE CLOCK EDGE
Current
X
L
X
H
L
→H–
4
(Stall)
SNOOZE MODE
None
X
H
X
High-Z
NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle
is executed first.
2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A
WRITE ABORT means a WRITE command is given, but no operation is performed.
3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off
the output drivers during a WRITE cycle. Some users may use OE# when the bus turn-on and turn-off times do not meet
their requirements.
4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs
during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE CLOCK
EDGE cycle.
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,
BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.
6. BWa# enables WRITEs to Byte “a” (DQas); BWb# enables WRITEs to Byte “b” (DQbs); BWc# enables WRITEs to
Byte “c” (DQcs); BWd# enables WRITEs to Byte “d” (DQds).
7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
8. Wait states are inserted by setting CKE# HIGH.
9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST cycle.
11. The address counter is incremented for all CONTINUE BURST cycles.
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