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參數(shù)資料
| 型號(hào)： | MT4C1004J |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 4 Meg x 1 FPM DRAM(4 M x 1快速頁面模式動(dòng)態(tài)RAM) |
| 中文描述： | 4梅格× 1快速頁面模式的DRAM（四米× 1快速頁面模式動(dòng)態(tài)內(nèi)存） |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 226K |
| 代理商： | MT4C1004J |
4 Meg x 1 FPM DRAM
D03.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
7
4 MEG x 1
FPM DRAM
OBSOLETE
without the
t
RCD limit,
t
AA and
t
CAC must always
be met.
15. The
t
RAD (MAX) limit is no longer specified.
t
RAD
(MAX) was specified as a reference point only. If
t
RAD was greater than the specified
t
RAD (MAX)
limit, then access time was controlled exclusively by
t
AA (
t
RAC and
t
CAC no longer applied). With or
without the
t
RAD (MAX) limit,
t
AA,
t
RAC and
t
CAC
must always be met.
16. Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
17.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
.
18.
t
WCS,
t
RWD,
t
AWD and
t
CWD are restrictive
operating parameters in LATE WRITE, READ
WRITE and READ-MODIFY-WRITE cycles only. If
t
WCS
≥
t
WCS (MIN), the cycle is an EARLY WRITE
cycle and the data output will remain an open circuit
through-out the entire cycle. If
t
RWD
≥
t
RWD (MIN),
t
AWD
≥
t
AWD (MIN) and
t
CWD
≥
t
CWD (MIN), the
cycle is a READ WRITE and the data output will
contain data read from the selected cell. If neither of
the above conditions is met, the cycle is a LATE
WRITE and the state of data-out is indeterminate (at
access time and until CAS# goes back to V
IH
).
19. These parameters are referenced to CAS# leading
edge in early WRITE cycles and WE# leading edge in
late WRITE or READ WRITE cycles.
20. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE# = LOW.
21. Extended refresh current is reduced as
t
RAS is
reduced from its maximum specification during the
extended refresh cycle.
22. The 3ns minimum is a parameter guaranteed by
design.
23. Column address changed once each cycle.
NOTES
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
CC
= 4.5V; f = 1 MHz.
3. I
CC
is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (0
°
C
≤
T
A
≤
70
°
C) is ensured.
6. An initial pause of 100
μ
s is required after power-up,
followed by eight RAS# refresh cycles (RAS# ONLY
or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the
t
REF refresh
requirement is exceeded.
7. AC characteristics assume
t
T = 5ns.
8. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
9. In addition to meeting the transition rate specifica-
tion, all input signals must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
10. If CAS# = V
IH
, data output is High-Z.
11. If CAS# = V
IL
, data output may contain data from the
last valid READ cycle.
12. Measured with a load equivalent to two TTL gates
and 100pF.
13. If CAS# is LOW at the falling edge of RAS#, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for
t
CP.
14. The
t
RCD (MAX) limit is no longer specified.
t
RCD
(MAX) was specified as a reference point only. If
t
RCD was greater than the specified
t
RCD (MAX)
limit, then access time was controlled exclusively by
t
CAC (
t
RAC [MIN] no longer applied). With or
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT4C1004J883C | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:4 MEG x 1 DRAM FAST PAGE MODE |
| MT4C1004JCN-100/883C | 制造商:Micross Components, Inc. 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-100/IT | 制造商:Micross Components 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-100/XT | 制造商:Micross Components 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-120/883C | 制造商:Micross Components, Inc. 功能描述:DRAM, 4MB - Rail/Tube |
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