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參數(shù)資料
| 型號： | MT4C1004J |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 4 Meg x 1 FPM DRAM(4 M x 1快速頁面模式動態(tài)RAM) |
| 中文描述： | 4梅格× 1快速頁面模式的DRAM（四米× 1快速頁面模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 226K |
| 代理商： | MT4C1004J |
4 Meg x 1 FPM DRAM
D03.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
2
4 MEG x 1
FPM DRAM
OBSOLETE
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RAS#
10
11
11
NO. 2 CLOCK
GENERATOR
REFRESH
CONTROLLER
NO. 1 CLOCK
GENERATOR
Vcc
Vss
10
D
REFRESH
COUNTER
WE#
CAS#
DATA-OUT
BUFFER
DATA-IN
BUFFER
11
Q
*EARLY WRITE
DETECTION CIRCUIT
1
COLUMN
ADDRESS
BUFFER(11)
ROW
ADDRESS
BUFFERS (11)
1024
1024
1024
R
(
2048
R
(
SENSE AMPLIFIERS
I/O GATING
2048 x 2048
MEMORY
ARRAY
2048
COLUMN
DECODER
R
D
C
S
*NOTE:
1. If WE# goes LOW prior to CAS# going LOW, EW detection circuit output is a HIGH (EARLY WRITE).
2. If CAS# goes LOW prior to WE# going LOW, EW detection circuit output is a LOW (LATE WRITE).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT4C4001STG-6 | standard or self refresh |
| MT4C4001STG-7 | standard or self refresh |
| MT4C4001STG-8 | standard or self refresh |
| MT4C4001JDJ-6 | standard or self refresh |
| MT4C4001SDJ-8 | standard or self refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT4C1004J883C | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:4 MEG x 1 DRAM FAST PAGE MODE |
| MT4C1004JCN-100/883C | 制造商:Micross Components, Inc. 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-100/IT | 制造商:Micross Components 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-100/XT | 制造商:Micross Components 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-120/883C | 制造商:Micross Components, Inc. 功能描述:DRAM, 4MB - Rail/Tube |
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