參數(shù)資料
型號(hào)： MT48H16M16LFFG
廠(chǎng)商： Micron Technology, Inc.
英文描述： MOBILE SDRAM
中文描述： 移動(dòng)SDRAM
文件頁(yè)數(shù)： 8/58頁(yè)
文件大?。?/td> 1451K
代理商： MT48H16M16LFFG
8
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x16
MOBILE SDRAM
ADVANCE
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
COL
n
NOP
COL
b
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
D
OUT
b
READ
X
= 0 cycles
NOTE:
Each READ command may be to either bank. DQM is LOW.
CAS Latency = 1
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL
n
NOP
BANK,
COL
b
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
D
OUT
b
READ
X
= 1 cycle
CAS Latency = 2
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL n
NOP
BANK,
COL
b
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
D
OUT
b
READ
NOP
T7
X
= 2 cycles
CAS Latency = 3
DON’T CARE
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Operating Mode
The normal operating mode is selected by setting
M7 and M8 to zero; the other combinations of values for
M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-
M2 applies to both READ and WRITE bursts; when M9
= 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (nonburst)
accesses.
CAS Latency
The CAS latency is the delay, in clock cycles, be-
tween the registration of a READ command and the
availability of the first piece of output data. The la-
tency can be set to two or three clocks.
If a READ command is registered at clock edge
n
,
and the latency is
m
clocks, the data will be available by
clock edge
n + m
. The DQs will start driving as a result of
the clock edge one cycle earlier (
n + m
- 1), and provided
that the relevant access times are met, the data will be
valid by clock edge
n + m
. For example, assuming that
the clock cycle time is such that all relevant access times
are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as
shown in Figure 2. Table 2 below indicates the operat-
ing frequencies at which each CAS latency setting can
be used.
Figure 2
CAS Latency
Table 2
CAS Latency
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
LATENCY = 1 LATENCY = 2 LATENCY = 3
≤
50
≤
100
≤
40
≤
83
CAS
CAS
SPEED
- 8
- 10
≤
125
≤
100
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