![](http://datasheet.mmic.net.cn/390000/MT46V4M32_datasheet_16823570/MT46V4M32_52.png)
52
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
Figure 28a
Data Output Timing –
t
DQSQ,
t
QH and Data Valid Window for TQFP Package
DQ (Last data valid)
DQ
6
DQ
6
DQ
6
DQ
6
DQ
6
DQ
6
DQS
1
DQ (Last data valid)
6
DQ (First data no longer valid)
6
DQ (First data no longer valid)
6
All DQs and DQS, collectively
5
NOTE:
1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an “early DQS,”
at T3 is a “nominal DQS,” and at T3n is a “l(fā)ate DQS.”
2. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and
ends with the last valid transition of DQs .
3. tQH is derived from tHP: tQH = tHP
4. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
5. The data valid window is derived for each DQS transitions and is defined as tQH minus tDQSQ.
6. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7, DQ8, DQ9, DQ10, DQ11, DQ13, DQ14, DQ15, DQ16, DQ17, DQ18, DQ19
DQ20, DQ21, DQ22, DQ23, DQ24, DQ25, DQ26, DQ27, DQ28, DQ29, DQ30, or DQ31.
Earliest signal transition
Latest signal transition
T2
T2
T2
T2n
T2n
T2n
T3
T3
T3
T3n
T3n
T3n
CK
CK#
T1
T2
T3
T4
T2n
T3n
tQH
3
tHP
4
tHP
4
tHP
4
tQH
3
tQH
3
tHP
4
tHP
4
tHP
4
tQH
3
tDQSQ
2
tDQSQ
2
tDQSQ
2
tDQSQ
2
Data
Valid
window
Data
Valid
window
Data
Valid
window
Data
Valid
window