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參數(shù)資料
| 型號： | MT46V4M32 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率的DDR SDRAM內存 |
| 文件頁數(shù)： | 44/66頁 |
| 文件大?。?/td> | 1921K |
| 代理商： | MT46V4M32 |
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44
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
I
DD
SPECIFICATIONS AND CONDITIONS
(Notes: 1-5, 10, 12, 14, 40; notes on pages 46-49) (0°C
≤
T
A
≤
+70°C; V
DD
Q = +2.5V ±0.125V, V
DD
= +2.5V ±0.125V)
PARAMETER/CONDITION
OPERATING CURRENT: One bank; Active-Precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice
per clock cyle; Address and control inputs changing once
per clock cycle;
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); I
OUT
= 0mA;
Address and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode;
t
CK =
t
CK MIN; CKE = LOW;
IDLE STANDBY CURRENT: CS# = HIGH; All banks idle;
t
CK =
t
CK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank; Active-Precharge;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN);
DQ, DM and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK (MIN); I
OUT
= 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle
AUTO REFRESH CURRENT
SYMBOL
I
DD
0
-33
TBD
-4
-5
UNITS NOTES
mA
TBD
TBD
22
I
DD
1
TBD
TBD
TBD
mA
22
I
DD
2P
TBD
TBD
TBD
mA
32
I
DD
2N
TBD
TBD
TBD
mA
I
DD
3P
TBD
TBD
TBD
mA
32
I
DD
3N
TBD
TBD
TBD
mA
22
I
DD
4R
TBD
TBD
TBD
mA
I
DD
4W
TBD
TBD
TBD
mA
t
RFC =
t
RFC (MIN)
t
RFC =
7.8μs
Standard
I
DD
5a
I
DD
5b
I
DD
6
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
22
27
11
SELF REFRESH CURRENT: CKE
≤
0.2V
MAX
CAPACITANCE
(Note: 13)
TQFP Package
FBGA Package
PARAMETER
Delta Input/Output Capacitance: DQs, DQS, DM
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, DQS, DM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
SYMBOL
DC
IO
DC
I
1
DC
I
2
C
IO
C
I
1
C
I
2
C
I
3
MIN
–
–
–
4.0
2.0
2.0
2.0
MAX
0.50
0.50
0.25
5.0
3.0
3.0
3.0
MIN
–
–
–
3.0
2.0
2.0
2.0
MAX
0.50
0.50
0.50
5.0
3.0
3.0
3.0
UNITS
pF
pF
pF
pF
pF
pF
pF
NOTES
24
29
29
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