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參數(shù)資料
| 型號： | MT46V4M32 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 13/66頁 |
| 文件大?。?/td> | 1921K |
| 代理商： | MT46V4M32 |
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13
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the DDR SDRAM and is analogous to CAS#-BEFORE-
RAS# (CBR) REFRESH in FPM/EDO DRAMs. This com-
mand is nonpersistent, so it must be issued each time
a refresh is required.
The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care”
during an AUTO REFRESH command. The 128 Mb x32
DDR SDRAM requires AUTO REFRESH cycles at an
average interval of 7.8μs (maximum).
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the abso-
lute refresh interval is provided. A maximum of eight
AUTO REFRESH commands can be posted to any given
DDR SDRAM, meaning that the maximum absolute
interval between any AUTO REFRESH command and
the next AUTO REFRESH command is 18 × 7.8μs
(140.4μs). This maximum absolute interval is to allow
future support for DLL updates internal to the DDR
SDRAM to be restricted to AUTO REFRESH cycles,
without allowing excessive drift in
t
AC between updates.
This is a JEDEC requirement that is
NOT
required for
Micron’s 128Mb x32 DDR device.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). The
DLL is automatically disabled upon entering SELF RE-
FRESH and is automatically enabled upon exiting SELF
REFRESH (200 clock cycles must then occur before a
READ command can be issued). Input signals except
CKE are “Don’t Care” during SELF REFRESH.
The procedure for exiting self refresh requires a se-
quence of commands. First, CK must be stable prior to
CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for
t
XSNR
because time is required for the completion of any in-
ternal refresh in progress. A simple algorithm for meet-
ing both refresh and DLL requirements is to apply
NOPs for 200 clock cycles before applying any other
command.
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| MT46V4M32LG | I.MX31 LITE KIT |
| MT46V64M4 | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4組,雙數(shù)據(jù)速率同步動態(tài)RAM) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V4M32LG | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M16 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE (DDR) SDRAM |
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