參數(shù)資料
型號: MT46V32M4TG-8
廠商: Micron Technology, Inc.
英文描述: DOUBLE DATA RATE DDR SDRAM
中文描述: 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存
文件頁數(shù): 56/68頁
文件大?。?/td> 2547K
代理商: MT46V32M4TG-8
56
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65
Rev. C; Pub. 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
128Mb: x4, x8, x16
DDR SDRAM
PRELIMINARY
Figure 29
x4, x8
Data Output Timing
t
DQSQ,
t
QH and Data Valid Window
DQ (Last data valid)
DQ
2
DQ
2
DQ
2
DQ
2
DQ
2
DQ
2
DQS
1
DQ (Last data valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
All DQs and DQS, collectively
6
NOTE:
1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an
early DQS,
at T3 is a
nominal DQS,
and at T3n is a "late DQS"
2. For a x4, only two DQs apply.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and
ends with the last valid transition of DQs .
4. tQH is derived from tHP : tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transitions and is defined as tQH minus tDQSQ.
Earliest signal transition
Latest signal transition
T2
T2
T2
T2n
T2n
T2n
T3
T3
T3
T3n
T3n
T3n
CK
CK#
T1
T2
T3
T4
T2n
T3n
tQH
4
tHP
5
tHP
5
tHP
5
tQH
4
tQH
4
tHP
5
tHP
5
tHP
5
tQH
4
tDQSQ
3
tDQSQ
3
tDQSQ
3
tDQSQ
3
Data
Valid
window
Data
Valid
window
Data
Valid
window
Data
Valid
window
QFC#
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