參數(shù)資料
型號(hào)： MT46V128M4P-75ZLIT:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
文件頁(yè)數(shù)： 74/94頁(yè)
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
76
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Notes
40.
VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width ≤ 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a
pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
41. VDD and VDDQ must track each other.
42. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
43. tRPST end point and tRPRE begin point are not referenced to a specific voltage level
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
44. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V.
Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V,
provided a minimum of 42Ω of series resistance is used between the VTT supply and
the input pin.
45. The current Micron part operates below 83 MHz (slowest specified JEDEC operating
frequency). As such, future die may not reflect this option.
46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
47. Random addressing changing 50 percent of data changing at every transfer.
48. Random addressing changing 100 percent of data changing at every transfer.
49. CKE must be active (HIGH) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC has been satisfied.
50. IDD2N specifies the DQ, DQS, and DM to be driven to a valid HIGH or LOW logic level.
IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to
remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
51. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset followed by 200 clock cycles before any READ command.
52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20MHz.
Any noise above 20 MHzat the DRAM generated from any source other than that of
the DRAM itself may not exceed the DC voltage range of 2.6V ±100mV.
53. The -6/-6T speed grades will operate with tRAS (MIN) = 40ns and tRAS (MAX) =
120,000ns at any slower frequency.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V128M4T67A3WC1 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays
MT46V128M4TG-5B/D 制造商:Samsung Semiconductor 功能描述:
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