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參數(shù)資料
| 型號： | MT46V128M4P-75L:C |
| 元件分類： | DRAM |
| 英文描述： | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 81/94頁 |
| 文件大?。?/td> | 4179K |
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
82
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Initialization
To ensure device operation the DRAM must be initialized as described below:
1. Simultaneously apply power to VDD and VDDQ.
2. Apply VREF and then VTT power.
3. Assert and hold CKE at a LVCMOS logic LOW.
4. Provide stable CLOCK signals.
5. Wait at least 200s.
6. Bring CKE HIGH and provide at least one NOP or DESELECT command. At this point
the CKE input changes from a LVCMOS input to a SSTL2 input only and will remain a
SSTL_2 input unless a power cycle occurs.
7. Perform a PRECHARGE ALL command.
8. Wait at least tRP time, during this time NOPs or DESELECT commands must be given.
9. Using the LMR command program the extended mode register (E0 = 0 to enable the
DLL and E1 = 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set
to 0; where n = most significant bit).
10. Wait at least tMRD time, only NOPs or DESELECT commands are allowed.
11. Using the LMR command program the mode register to set operating parameters and
to reset the DLL. At least 200 clock cycles are required between a DLL reset and any
READ command.
12. Wait at least tMRD time, only NOPs or DESELECT commands are allowed.
13. Issue a PRECHARGE ALL command.
14. Wait at least tRP time, only NOPs or DESELECT commands are allowed.
15. Issue an AUTO REFRESH command. This may be moved prior to step 13.
16. Wait at least tRFC time, only NOPs or DESELECT commands are allowed.
17. Issue an AUTO REFRESH command. This may be moved prior to step 13.
18. Wait at least tRFC time, only NOPs or DESELECT commands are allowed.
19. Although not required by the Micron device, JEDEC requires a LMR command to clear
the DLL bit (set M8 = 0). If a LMR command is issued the same operating parameters
should be utilized as in step 11.
20. Wait at least tMRD time, only NOPs or DESELECT commands are allowed.
21. At this point the DRAM is ready for any valid command. At least 200 clock cycles with
CKE HIGH are required between step 11 (DLL RESET) and any READ command.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MT46V128M4T67A3WC1 | 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays |
| MT46V128M4TG-5B/D | 制造商:Samsung Semiconductor 功能描述: |
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