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參數(shù)資料
| 型號(hào)： | MT46V128M4P-75L:C |
| 元件分類： | DRAM |
| 英文描述： | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 69/94頁 |
| 文件大?。?/td> | 4179K |
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09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
71
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified.
3. Outputs (except for IDD measurements) measured with equivalent load:
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environ-
ment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#),
and parameter specifications are guaranteed for the specified AC input levels under
normal use conditions. The minimum slew rate for the input signals used to test the
device is 1V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e.,
the receiver will effectively switch as a result of the signal crossing the AC input level,
and will remain in that state as long as the signal does not ring back above [below] the
DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in
the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not
exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC
error and an additional ±25mV for AC noise. This measurement is to be taken at the
nearest VREF bypass capacitor.
7. VTT is not applied directly to the device. VTT is a system supply for signal termination
resistors, is expected to be set equal to VREF and must track variations in the DC level
of VREF.
8. VID is the magnitude of the difference between the input level on CK and the input
level on CK#.
9. The value of VIX and VMP are expected to equal VDDQ/2 of the transmitting device and
must track variations in the DC level of the same.
10. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle times at CL = 3 for -5B, CL = 2.5 for -6/-6T/-75, and CL = 2 for -
75E/-75Z speeds with the outputs open.
11. Enables on-chip refresh and address counters.
12. IDD specifications are tested after the device is properly initialized, and is averaged at
the defined cycle rate.
13. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100
MHz, TA = 25°C, VOUT(DC) = VDDQ/2, V(peak-to-peak) = 0.2V. DM input is
grouped with I/O pins, reflecting the fact that they are matched in loading.
14. For slew rates less than 1V/ns and greater than or equal to 0.5V/ns. If the slew rate is
less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/
ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains
constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. For -5B, -6, and
-6T, slew rates must be greater than or equal to 0.5V/ns.
15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
VREF.
Output
(VOUT)
Reference
Point
50Ω
VTT
30pF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V128M4T67A3WC1 | 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays |
| MT46V128M4TG-5B/D | 制造商:Samsung Semiconductor 功能描述: |
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