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參數(shù)資料
| 型號： | MT28F321P18FG-90BET |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 1.8V PROM, 90 ns, PBGA48 |
| 封裝： | FBGA-48 |
| 文件頁數(shù)： | 34/35頁 |
| 文件大?。?/td> | 386K |
| 代理商： | MT28F321P18FG-90BET |
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8
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
COMMAND STATE MACHINE (CSM)
Commands are issued to the command state ma-
chine (CSM) using standard microprocessor write tim-
ings. The CSM acts as an interface between external
microprocessors and the internal WSM. The available
commands are listed in Table 3, their definitions are
given in Table 4, and their descriptions in Table 5.
Program and erase algorithms are automated by an
on-chip WSM. For more specific information about the
CSM transition states, see Micron technical note
TN-28-33, “Command State Machine Description and
Command Definition.”
Once a valid PROGRAM/ERASE command is en-
tered, the WSM executes the appropriate algorithm,
which generates the necessary timing signals to con-
trol the device internally and accomplish the requested
operation. A command is valid only if the exact se-
quence of WRITEs is completed. After the WSM com-
pletes its task, the WSM status bit (SR7) (see Table 7) is
set to a logic HIGH level (1), allowing the CSM to re-
spond to the full command set again.
OPERATIONS
Device operations are selected by entering a stan-
dard JEDEC 8-bit command code with conventional
microprocessor timings into an on-chip CSM through
I/Os DQ0–DQ7. The number of bus cycles required to
activate a command is typically one or two. The first
operation is always a WRITE. Control signals CE# and
WE# must be at a logic LOW level (VIL), and OE# and
RST# must be at logic HIGH (VIH). The second opera-
tion, when needed, can be a WRITE or a READ depend-
ing upon the command. During a READ operation,
control signals CE# and OE# must be at a logic LOW
level (VIL), and WE# and RST# must be at logic HIGH
(VIH).
Table 6 shows the bus operations for all the modes:
write, read, reset, standby, and output disable.
When the device is powered up, internal reset cir-
cuitry initializes the chip to a read array mode of opera-
tion. Changing the mode of operation requires that a
command code be entered into the CSM. For each one
of the two memory partitions, an on-chip status regis-
ter is available. These two registers allow the progress
of the various operations that can take place on a
memory bank to be monitored. One of the two status
registers is interrogated by entering a READ STATUS
REGISTER command onto the CSM (cycle 1), specify-
ing an address within the memory partition boundary,
and reading the register data on I/Os DQ0–DQ7
(cycle 2). Status register bits SR0-SR7 correspond to
DQ0–DQ7 (see Table 7).
COMMAND DEFINITION
Once a specific command code has been entered,
the WSM executes an internal algorithm, generating
the necessary timing signals to program, erase, and
verify data. See Table 4 for the CSM command defini-
tions and data for each of the bus cycles.
STATUS REGISTER
The status register allows the user to determine
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling OE# and CE#, and reading the resulting
status code on I/Os DQ0–DQ7. The high-order I/Os
(DQ8–DQ15) are set to 00h internally, so only the low-
Table 3
Command State Machine Codes For Device Mode Selection
COMMAND DQ0–DQ7
CODE ON DEVICE MODE
40h/10h
Program setup/alternate program setup
20h
Block erase setup
50h
Clear status register
60h
Protection configuration setup
70h
Read status register
90h
Read protection configuration register
98h
Read query
B0h
Program/erase suspend
C0h
Protection register program/lock
D0h
Program/erase resume – erase confirm
FFh
Read array
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