參數(shù)資料
型號(hào): MT28F321P18FG-90BET
元件分類: PROM
英文描述: 2M X 16 FLASH 1.8V PROM, 90 ns, PBGA48
封裝: FBGA-48
文件頁數(shù): 14/35頁
文件大?。?/td> 386K
代理商: MT28F321P18FG-90BET
21
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
READING THE CHIP PROTECTION REGISTER
The chip protection register is read in the device
identification mode. To enter this mode, load the 90h
command to the bank containing address 00h. Once in
this mode, READ cycles from addresses shown in Table
9 retrieve the specified information. To return to the
read array mode, write the READ ARRAY command
(FFh). The READ ARRAY command, FFh, must be is-
sued to the bank containing address 00h prior to issu-
ing other commands.
PROGRAMMING THE CHIP PROTECTION
REGISTER
The first 64 bits (PR1) of the protection register (ad-
dresses 81h–84h) are programmed with a unique iden-
tifier at the factory. DQ0 of the PR lock register (address
80h) is programmed to a “0” state, locking the first 64
bits and preventing any further programming. The
second 64 bits (PR2) is a user area (addresses 85h–
88h), where the user can program any information into
this area as long as DQ1 of the PR lock register remains
unprogrammed. After DQ1 of the PR lock register is
programmed, no further programming is allowed on
PR2. The programming sequence is similar to array
programming except that the PROTECTION REGIS-
TER PROGRAMMING SETUP command (C0h) is issued
instead of an ARRAY PROGRAMMING SETUP com-
mand (40h), followed by the data to be programmed at
addresses 85h–88h.
To program the PR lock bit for PR2 (to prevent fur-
ther programming), use the above sequence on ad-
dress 80h, with data of FFFDh (DQ1 = 0).
ASYNCHRONOUS READ CYCLE
When accessing addresses in a random order or
when switching between pages, the access time is given
by tAA.
When CE# and OE# are LOW, the data is placed on
the data bus and the processor can read the data.
PAGE READ MODE
The initial portion of the page mode cycle is the
same as the asynchronous access cycle. Holding CE#
LOW and toggling addresses A0–A2 allows random ac-
cess of other words in the page. The page word size is
eight words.
VPP / VCC PROGRAM AND ERASE
VOLTAGES
The MT28F321P20 Flash memory provides in-
system programming and erase with VPP in the
0.9V–2.2V range. The 12V VPP mode programming is
offered for compatibility with existing programming
equipment and does not enhance program/erase
performance.
The device can withstand 100,000 WRITE/ERASE
operations when VPP = VPP1 or 100 WRITE/ERASE opera-
tions and 10 cumulative hours when VPP = VPP2.
In addition to the flexible block locking, the VPP
programming voltage can be held low for absolute hard-
ware write protection of all blocks in the Flash device.
When VPP is below VPPLK, any PROGRAM or ERASE
operation will result in an error, prompting the corre-
sponding status register bit (SR3) to be set.
During WRITE and ERASE operations, the WSM
monitors the VPP voltage level. WRITE/ERASE opera-
tions are allowed only when VPP is within the ranges
specified in Table 10.
When VCC is below VLKO, any WRITE/ERASE opera-
tion will be disabled.
Table 10
VPP Range (V)
MIN
MAX
In-System
0.9
2.2
In-Factory
11.4
12.6
相關(guān)PDF資料
PDF描述
MT28F640J3BS-12MET 4M X 16 FLASH 2.7V PROM, 120 ns, PBGA64
MT29F4G08FABWGXXXXET 512M X 8 FLASH 2.7V PROM, PDSO48
MT2LSYT3272T1G-11P 32K X 72 CACHE SRAM MODULE, 11 ns, DMA160
MT2LSYT3272T1G-12P 32K X 72 CACHE SRAM MODULE, 12 ns, DMA160
MT333X GENERAL PURPOSE AUDIO CONNECTOR, JACK
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT28F321P20 制造商:MICRON 制造商全稱:Micron Technology 功能描述:FLASH MEMORY
MT28F322D18 制造商:MICRON 制造商全稱:Micron Technology 功能描述:FLASH MEMORY
MT28F322D18FH-704BET 制造商:MICRON 制造商全稱:Micron Technology 功能描述:FLASH MEMORY
MT28F322D18FH-704TET 制造商:MICRON 制造商全稱:Micron Technology 功能描述:FLASH MEMORY
MT28F322D18FH-705BET 制造商:MICRON 制造商全稱:Micron Technology 功能描述:FLASH MEMORY