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參數(shù)資料
| 型號(hào)： | MT28F321P18FG-90BET |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 1.8V PROM, 90 ns, PBGA48 |
| 封裝： | FBGA-48 |
| 文件頁數(shù)： | 3/35頁 |
| 文件大?。?/td> | 386K |
| 代理商： | MT28F321P18FG-90BET |
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11
2 Meg x 16 Page Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16
PAGE FLASH MEMORY
PRELIMINARY
Table 5
Command Descriptions (continued)
CODE DEVICE MODE
BUS CYCLE
DESCRIPTION
D0h
Erase Confirm
Second
If the previous command was an ERASE SETUP command, then the
CSM will close the address and data latches, and it will begin erasing
the block indicated on the address balls. During programming/erase,
the device will respond only to the READ STATUS REGISTER,
PROGRAM SUSPEND, or ERASE SUSPEND commands and will output
status register data on the falling edge of OE# or CE#, whichever
occurs last.
Program/Erase
First
If a PROGRAM or ERASE operation was previously suspended, this
Resume
command will resume the operation.
FFh
Read Array
First
During the array mode, array data will be output on the data bus.
01h
Lock Block
Second
If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and lock the block indicated on the
address bus.
2Fh
Lock Down
Second
If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and lock down the block indicated on
the address bus.
D0h
Unlock Block
Second
If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and unlock the block indicated on the
address bus. If the block had been previously set to lock down, this
operation will have no effect.
00h
Invalid /Reserved
Unassigned command that should not be used.
mand set. The CSM stays in the current command state
until the microprocessor issues another command.
The WSM successfully initiates an ERASE or PRO-
GRAM operation only when VPP is within its correct volt-
age range.
CLEAR STATUS REGISTER
The internal circuitry can set, but not clear, the block
lock status bit (SR1), the VPP status bit (SR3), the pro-
gram status bit (SR4), and the erase status bit (SR5) of
the status register. The CLEAR STATUS REGISTER com-
mand (50h) allows the external microprocessor to clear
these status bits and synchronize to the internal op-
erations. When the status bits are cleared, the device
returns to the read array mode.
READ OPERATIONS
The following READ operations are available: READ
ARRAY, READ PROTECTION CONFIGURATION REG-
ISTER, READ QUERY and READ STATUS REGISTER.
READ ARRAY
The array is read by entering the command code
FFh on DQ0–DQ7. Control signals CE# and OE# must
be at a logic LOW level (VIL), and WE# and RST# must be
at logic HIGH level (VIH) to read data from the array.
Data is available on DQ0–DQ15. Any valid address
within any of the blocks selects that address and allows
data to be read from that address. Upon initial power-
up or device reset, the device defaults to the read array
mode.
READ PROTECTION CONFIGURATION DATA
The chip identification mode outputs three types
of information: the manufacturer/device identifier, the
block locking status, and the protection register. Two
bus cycles are required for this operation: the chip iden-
tification data is read by entering the command code
90h on DQ0–DQ7 to the bank containing address 00h
and the identification code address on the address
lines. Control signals CE# and OE# must be at a logic
LOW level (VIL), and WE# and RST# must be at a logic
HIGH level (VIH) to read data from the protection con-
figuration register. Data is available on DQ0–DQ15.
After data is read from the protection configuration
register, the READ ARRAY command, FFh, must be is-
sued to the bank containing address 00h prior to issu-
ing other commands. See Table 9 for further details.
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