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| 型號： | MT28C3224P20 |
| 廠商： | Micron Technology, Inc. |
| 元件分類： | DRAM |
| 英文描述： | FLASH AND SRAM COMBO MEMORY |
| 中文描述： | 閃存和SRAM式內(nèi)存 |
| 文件頁數(shù)： | 1/42頁 |
| 文件大?。?/td> | 498K |
| 代理商： | MT28C3224P20 |
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1
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
ADVANCE
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
FLASH AND SRAM
COMBO MEMORY
MT28C3224P20
MT28C3224P18
Low Voltage, Extended Temperature
0.18μm Process Technology
FEATURES
Flexible dual-bank architecture
Support for true concurrent operations with no
latency:
Read bank
b
during program bank
a
and vice versa
Read bank
b
during erase bank
a
and vice versa
Organization: 2,048K x 16 (Flash)
256K x 16 (SRAM)
Basic configuration:
Flash
Bank
a
(8Mb Flash for data storage)
– Eight 4K-word parameter blocks
– Fifteen 32K-word blocks
Bank
b
(24Mb Flash for program storage)
– Forty-eight 32K-word main blocks
SRAM
4Mb SRAM for data storage
–
256K-words
F_V
CC
, V
CC
Q, F_V
PP
, S_V
CC
voltages
MT28C3224P20
1.80V (MIN)/2.20V (MAX) F_V
CC
read voltage
1.80V (MIN)/2.20V (MAX) S_V
CC
read voltage
1.80V (MIN)/2.20V (MAX) V
CC
Q
MT28C3224P18
1.70V (MIN)/1.90V (MAX) F_V
CC
read voltage
1.70V (MIN)/1.90V (MAX) S_V
CC
read voltage
1.70V (MIN)/1.90V (MAX) V
CC
Q
MT28C3224P20/P18
1.80V (TYP) F_V
PP
(in-system PROGRAM/ERASE)
1.0V (MIN) S_V
CC
(SRAM data retention)
12V ±5% (HV) F_V
PP
(production programming
compatibility)
Asynchronous access time
Flash access time: 80ns @ 1.80V F_V
CC
SRAM access time: 85ns @ 1.80V S_V
CC
Page Mode read access
Interpage read access: 80ns @ 1.80V F_V
CC
Intrapage read access: 30ns @ 1.80V F_V
CC
Low power consumption
Enhanced suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
Read/Write SRAM during program/erase of Flash
Dual 64-bit chip protection registers for security
purposes
PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
Cross-compatible command set support
Extended command set
Common flash interface (CFI) compliant
OPTIONS
Timing
80ns
85ns
Boot Block Configuration
Top
Bottom
Operating Voltage Range
V
CC
= 1.70V–1.90V
V
CC
= 1.80V–2.20V
Operating Temperature Range
Commercial (0
o
C to +70
o
C)
Extended (-40
o
C to +85
o
C)
Package
66-ball FBGA (8 x 8 grid)
MARKING
-80
-85
T
B
18
20
None
ET
FL
Part Number Example:
MT28C3224P20FL-80 BET
BALL ASSIGNMENT
66-Ball FBGA (Top View)
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
8
9
10
11
12
Top View
(Ball Down)
NC
NC
A14
A9
DQ11
A6
A0
A15
A10
A19
S_OE#
A7
A4
A20
A16
F_WE#
S_V
SS
F_WP#
S_LB#
A18
F_V
CC
A12
S_WE#
DQ6
S_CE2
DQ10
DQ8
A2
F_V
SS
F_V
SS
DQ14
DQ4
S_V
CC
DQ2
DQ0
A1
F_OE#
V
cc
Q
DQ7
DQ5
F_V
CC
DQ3
DQ1
S_CE1#
NC
NC
NC
NC
NC
A13
DQ15
DQ13
DQ12
DQ9
A3
F_CE#
NC
NC
A11
A8
NC
F_RP#
F_V
PP
S_UB#
A17
A5
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT28C3224P20FL-80 BET | 制造商:Micron Technology Inc 功能描述: |
| MT28C3224P20FL-80 BET TR | 制造商:Micron Technology Inc 功能描述: |
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